Portable data acquisition system composed of ADuC812 and K9S6408V0A

    Abstract: K9S6408V0A is a flash memory produced by Samsung. It has the characteristics of large capacity and simple interface. The ADuC812 is a multi-channel 12-bit AD converter with embedded MCU. This article introduces a portable data acquisition system based on ADuC812 and equipped with K9S6408V0A flash memory, and provides the hardware interface and software programming of AduC812 and K9S6408V0A.

    ADuC812 is a multi-channel 12-bit AD converter with built-in MCU produced by AD Company. K9S6408V0A is Samsung's new FLASH memory with a capacity of up to 64M. It only needs 3V power supply for reading, programming, erasing and other operations, and The interface to the CPU is simple. The data acquisition system composed of K9S6408V0A and ADuC812 has the characteristics of small size and low power consumption.

    ADuC812 is a fully integrated 12-bit data acquisition system that contains a high-performance self-calibrating multi-channel ADC and two 12-bit DACs and an 8-bit 8051-compatible MCU in a single chip. ADuC812 itself has 8k bytes of Flash program memory, 640 bytes of Flash data memory and 256 bytes of data SRAM. In addition, the MCU also supports DMA functions such as watchdog timer, power monitor and ADC. It also provides 32 programmable I/O lines, I2C-compatible SPI and standard UART serial port I/O for multi-processor interface and I/O expansion. Its MCU core and analog converter have normal, idle and power-down operating modes, providing a flexible power management solution suitable for low-power applications.

    All parts of the AD conversion module of ADuC812 can be easily set through 3 SFRs.

    Therefore, it can be seen that ADuC812 itself is a high-performance multi-channel data acquisition system with embedded MCU, but the internal data memory capacity is limited. If a data acquisition system that stores large amounts of data is required, an external data memory can be connected. The system introduced in this article belongs to this type of system, and an external data memory can be connected. The system introduced in this article belongs to this type of system. It is designed using an external K9s6408V0A flash memory, and its data capacity can reach 8M bytes.

1 Introduction to K9S6408V0A

    K9S6408V0A is a 22-pin surface-mounted device with an internal (8M+256k) bit × 8-bit storage space, which can be organized into 16384 rows and 528 columns. The backup 16 columns have column address codes from 513 to 527. It can perform reading and writing of 528 bytes per page and erase operations of 8k bytes per block. A 528-bit data register can be used for data conversion of memory cells during page read or page program operations.

    The outstanding advantage of K9S6408V0A is that its command, address and data information are transmitted through 8 I/O lines, and the address line for addressing the memory unit is not used as a pin of the chip. The 23-bit address is written into the address register three times, and the corresponding unit is found after decoding. For microcontrollers, when the required storage space exceeds 64k, there are certain difficulties in addressing, and the system wiring is complicated and the reliability is low. The use of this flash memory can not only overcome the above difficulties, but also facilitate upgrades to larger capacities without changing external connections. Figure 1 is its functional block diagram. The signal line functions are as follows:

    CLE: Command latch enable. When it is high, the command is latched into the command register through the I/O port on the rising edge of the WE signal.

    ALE: Address latch enable. When it is high, the address is latched into the address register on the rising edge of the WE signal; when it is low, the input data is latched.

    CE: Film Selection. During a read operation, CE goes high and the device enters standby mode; during programming or erasing, the device is busy and CE high is ignored.

    WE: Write enable. Command, address and data are latched on the rising edge of the WE signal.

    RE: Read enable. Valid on falling edge.

    WP: Write protected. During supply voltage transitions, when WP is low, write/erase protection will occur.

    R/B: Operation status indication. When it is low, it indicates that a programming, erasing or reading operation is in progress. After the operation is completed, it becomes high, which is an open circuit output.

    I/O port: (I/O0~I/O7) three-state. Outputs commands, addresses and data, and outputs data during read operations.

2 Interface between ADuC812 and K9S6408V0A

    The connection between K9S6408V0A and ADuC812 is very simple and provides good conditions for future upgrades. The basic hardware interface circuit is shown in Figure 2. When connecting, use P3.0~P3.3 of the P3 port of ADuC812 to connect to CE, CLE, ALE and R/B of K9S6408V0A respectively. I/O0~I/O7 of K9S6408V0A are connected to P0.0~P0 of ADuC812 respectively. .7, RE and WE of K9S6408V0A are connected to RD (P3.7) and WE (P3.6) of ADuC812 respectively, while the P1 port (analog input port) of ADuC812 is connected to the data acquisition sensor. This constitutes a data collection system. ADuC812 is responsible for acquisition, while K9S6408V0A is responsible for storing data. The various operations of K9S6408V0A have common characteristics, that is, the operation command word is first sent to the command register on the I/O port, and then the address of the unit to be operated is sent in three consecutive cycles (the order is A0~A7, A9~A16, A17~ A22, where A8 is determined by the command word). Table 1 is its command set.

Table 1 Command set

    Taking the page programming operation as an example, the standard assembly programming method of K9S6408V0A is given below. The methods of page reading and block erasing are similar to page programming, except that the data is latched by RE during reading, and only two cycles of addresses are sent during erasing. The page programming operation can write data to one or several cells. The following is the procedure for the page programming operation:

    Entrance address:

    R1, R2, R3 - the column address and page address of the unit where the data is to be written;

    R7-The number of written data

    R0-source data pointer

    R6-failure flag

    START: MOV DPTR, #XXXXH; address

    CLR P3.0;Chip Select

    CLR P3.2; Clear ALE

    SETB P3.1; Set CLE

    MOV A, #80H

    MOVK@DPTR,A; command 80H

    CLR P3.1; clear CLE

    SETB P3.2; Set ALE

    MOV A,R1

    MOVX@DPTR,A

    MOV A,R2

    MOVX@DPTR,A

    MOV A, R3

    MOVX@DPTR, A; output address A0-A22

    CLR P3.2; Clear ALE

    PR1: MOVX A,@R0

    MOVX@DPTR,A

    DJNZ R7, PR1; cycle writing

    SETB P3.1; Set CLE

    MOV A, #10H

    MOVX@DPTR,A; command 10H

    PRAM2:MOV C,P3.3

    JNC PRAM2 ;busy, loop

    SETB P3.1; Set CLE

    MOV A, #70H

    MOVX@DPTR, A; Command 70H,

    CLR P3.1; clear CLE

    MOVX A, @DPTR; read status

    JNB ACC.0, SUC; SR.0=0, success

    ERR: MOV R6, #0FH

    SUC: SETB P3.0

    END

3 system software

    This data acquisition system is an 8-channel sequential acquisition, the clock frequency of ADuC812 is 11.0592MHz, and the CPU manages the A/D converter in interrupt mode. When the A/D conversion is completed, a request signal is sent to the CPU, and the CPU responds to the interrupt. The interrupt processing subroutine is responsible for reading the converted data and storing it to K9S6408V0A. Then the channel number is increased by 1, and the corresponding Flash memory address is also increased. 1. Figure 3 and Figure 4 are flow charts of the system main program and interrupt processing subroutine respectively.

    The main program and A/D interrupt processing subroutine of this system are given below in standard assembly language.

    ORG 0000H

    FLAG EQU 60H; external memory full flag

    CHAN EQU 61H; Channel number

    JMP MAIN

    ;;The following is the interrupt processing subroutine

    ORG 0033H; A/D interrupt handler entry address

    CLR EA; turn off interrupts

    MOV R0, ADCDATAH; the high 8 bits of the conversion result are sent to R0

    LCALL WRITEONE; Write a data to the external Flash RAM program, please refer to the page programming program segment given above;

    INC R1; add 1 to the low-order address

    CJNE R1, #0FFH, NEXT; if it is not out of range, process the next one

    MOV R1, #00H; if it exceeds the range, the low-order address will be cleared to zero.

    INC R2; add 1 to the intermediate address

    CJNE R2, #0FFH, NEXT; if it is not out of range, process the next one

    MOV R2, #00H; out of range, the middle address is cleared

    INC R3; add 1 to the high-order address

    CJNE R3, #03FH, NEXT; if the range is not exceeded, process the next one

    MOV FLAG, #01H; otherwise, standard position 1

    SJMP RET1; return

    NEXT: MOV R0, #ADCDATAL; the lower 8 bits of the conversion result are sent to R0

    LCALL WRITEONE; write a data

    LCALL WRITEONE; write a data

    INC CHAN; channel number plus 1

    CJNE CHAN, #08H, CHANG; if the channel number is not equal to 8, start the next channel conversion

    MOV CHAN, #00H; otherwise the channel number is cleared to zero

    CHANG: MOV ADCCON1, #07Ch; start A/D conversion

    MOV ADCCON2, #CHAN; select conversion channel

    SETB EA; interrupt enable

    ETB EADC; enable A/D conversion interrupt

    SETB ADC1

    RET1; RETI; interrupt return

    ORG 1000H

    ;;The following is the main program

    MAIN:

    MOV AFLAG, #00H; Flag cleared

    MOV CHAN, #00H; clear channel number

    MOV ADCCON1, #07CH; Start A/D conversion, one conversion time is 14.5μs

    MOV ADCCON2, #CHAN; select conversion channel

    MOV R1, #00H

    MOV R2, #00H

    MOV R3, #00H; External memory address initialization

    SETB EA; interrupt enable

    SETB EADC; enable A/D conversion interrupt

    SETB ADC1 ; Start a single conversion cycle

    HERE: SETB PCON.0; CPU enters idle mode, power consumption is reduced; low interrupt wake-up

    MOV A, FLAG

    JNZ HERE ;wait if memory is not full

    END

4 Conclusion

    In summary, the software and hardware design of the data acquisition system described in this article has the characteristics of fast acquisition speed, large storage capacity, small system size and low power consumption, and is suitable for portable low-power applications. As long as the program is slightly modified, it can be used in a variety of situations, and the collected data can also be analyzed and processed in real time, making the system an intelligent data collection and analysis system.