Application of ISPl362 in infrared imaging system based on FPGA

Application of ISPl362 in infrared imaging system based on FPGA

Abstract: ISP1362 is a USB programmable control chip launched by Philips. It integrates an advanced host controller and a peripheral controller. The host and device controllers are compatible with USB 2.0 protocol and support 12 Mb/s full-speed transmission and 1.5 Mb/s low-speed transmission. The chip has three working modes, namely host controller mode, device controller mode and OTG mode. This paper mainly focuses on the application of USB control chip ISP1362 in data acquisition of infrared imaging system based on FPGA. Verilog HDL language is used to complete its functions in device controller mode, which has good portability.
Keywords: FPGA; ISP1362; USB interface; firmware; Verilog HDL

O Introduction
In recent years, infrared thermal imaging systems have been increasingly used in military and industrial applications, so the study of infrared images has become a hot topic. In order to meet the needs of many real-time image processing methods, image processing systems have increasingly higher requirements for the speed and accuracy of image data acquisition. Traditional interfaces, such as ISA interface, PCI interface, PS/2 interface, etc., are non-shared interfaces, which are not only bulky, but also have different specifications. The USB interface overcomes the above-mentioned defects of traditional interfaces and has the advantages of high speed, bidirectionality, low cost, good compatibility, and strong versatility. It has been widely used in various IT fields. At the same time, various types of USB interface control chips have also emerged. The ISPl362 chip has also attracted widespread attention from users for its low cost, high reliability, low power consumption, and easy expansion. ISPl362 consists of a host controller, a device controller, an OTG controller, a USB transceiver, an OTG transceiver, and registers. Among them, the OTG controller mainly provides all OTG controls including monitoring and conversion functions. In OTG mode, it can be used as both a host and a peripheral, and supports the Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). Considering the need to further improve the system in the future, this chip is selected to complete the design of the USB interface. There is no MCU integrated inside the chip. The design uses Altera's Field-Programmabte Gate Arrav (FPGA) EP2C70-F672C6 to control the normal operation of the chip, which is simple and reliable to operate. EP2C70F672C6 has the advantages of low power consumption, high density and low cost. It can provide 4608 to 68416 logic units, including up to 150 embedded 18×18-bit multipliers, dedicated external memory interface circuits, and the highest operating frequency can reach 260 MHz. Based on the above reasons, this FPGA chip is selected to implement various functions in the infrared imaging system.

l Infrared imaging system
The functional block diagram of the infrared imaging system is shown in Figure 1. The entire system function is implemented on the FPGA. After the system is powered on, the FPGA is configured, and the infrared focal plane detector responds to the infrared target radiation under the action of the driving signal, converts the radiation signal into an analog voltage signal output; the A/D conversion module converts the analog voltage signal into a digital signal, and after non-uniformity correction, blind pixel processing and other processes, the data is stored in the FPGA external memory. The main task of this work is to transfer the data in the memory to the PC through the USB interface, so that the data can be further processed as needed.

2 USB firmware structure design
The USB firmware structure design includes the enumeration process and the data transmission process. The data transmission process is similar to the processing method of the in interrupt in the enumeration process. Therefore, this article mainly introduces the firmware writing of the enumeration process.
The flowchart of the enumeration process is shown in Figure 2.

The enumeration process is the process in which the host identifies the device by sending a series of requests to the device. USB defines a total of 11 standard USB requests, some of which are required. For example, the host must obtain the device descriptor, interface descriptor, and endpoint descriptor of the device through the Get Descriptor request to identify the device; a unique non-zero address must be assigned to the device through the Set Address request so that the host can identify the device and transfer data to the device; a non-zero configuration value must be assigned to the device through the Set Configuration request. USB requests can only be transmitted using the control pipe. Before the host identifies what kind of device is connected, it will assign a default address of O to the unknown device. The host communicates with the device through the 0 address until the host determines that a device is actually connected, and then assigns a unique non-zero address to the device. After that, the host can communicate with the device through this non-zero address, including obtaining all the configuration information and interface information of the device and completing the final data transfer.
2.1 Chip initialization
The initialization of the chip mainly includes the operation mode, speed selection, and register configuration. The selection of the working mode can be achieved by setting the 62nd pin A1 of ISPl362 to a high level. What is realized here is full-speed data transmission. The following mainly introduces the configuration of registers.

There are more than 40 registers inside the ISPl362 device controller. The key work when writing code is to determine the configuration value according to the meaning of each bit of the register, especially some key bits, only correct configuration can ensure the normal operation of the chip. Before using ISPl362, the registers to be configured first include mode register, hardware configuration register, interrupt enable register, etc. The endpoint configuration register can be completed at any time, but it is only valid after initialization after enumeration. In order to facilitate program design, at the beginning, the 16 endpoint configuration registers are also configured while configuring the mode register, hardware configuration register, interrupt enable register, etc. Endpoint 0 is a control endpoint, including in and out endpoints. The size of these two endpoints is fixed, both 64 B. The enumeration process is carried out through this endpoint. The remaining 14 are programmable endpoints, which can also be configured as double-buffered endpoints to further improve throughput. In the design, endpoint 1 is configured as a 64 B double-buffered bulk in endpoint; endpoint 2 is configured as a 16 B interrupt out endpoint; endpoint 3 is configured as a 16 B interrupt in endpoint, etc.; unused endpoints can be disabled. When configuring the mode register, it is particularly important to note that all interrupts can be enabled through the third bit. For the hardware configuration register, pay attention to the setting of the interrupt output pin INT2. Here, select the low-level effective interrupt signal mode. After these registers are correctly configured, ISP1362 will enter the expected working mode.
Since there are many registers that need to be configured in ISP1362, this design first generates a 16-bit ROM with a size of 128 B in FPGA, and then writes the write commands and configuration values ​​of the registers to be configured into the ROM in sequence. When configuring, just write the data in the ROM into the chip in sequence. The configuration timing of the register is shown in Figure 3 (for easy observation, only part of the register configuration is captured in Figure 3).

In Figure 3, signal clk_50M is the global clock; ISP_Rst is the reset signal of the chip; ISP_CS, ISP_WR, and ISP_RD are the chip select signal, read signal, and write signal of ISP1362, respectively, and are all valid at low level; ISP_Al is the mode selection signal. When its value is 1, the chip works in the device controller mode, and when it is 0, the chip works in the host controller mode; when ISP_A0 is high, the corresponding ISP_Data is the initialization command of DC, and when ISP_AO is low, the corresponding ISP_Data is the configuration value written to the corresponding register.
2.2 Device reception request
Each request from the host is sent to the out buffer of the out endpoint in the form of a setup packet. When the out buffer receives data, an interrupt will be generated on the INT2 pin of the chip. After the mode register, hardware configuration register, and interrupt enable register are correctly configured, when an interrupt event occurs, the SIE inside ISP1362 can detect the interrupt and set the corresponding bit of the interrupt register to a high level. The firmware determines the interrupt type by reading and analyzing the value of the interrupt register, and then handles the interrupt event.
The first interrupt detected by the firmware is the out interrupt. This is because after the power-on reset, the host sends the first setup request packet to the out buffer. When the out interrupt is received, the firmware first reads the endpoint status register of the out endpoint to clear the interrupt so that the chip can receive other interrupts. Then the firmware determines whether the out buffer contains a setup packet based on the value of the endpoint status register, and then reads the out buffer.
The content of the out buffer determines what kind of request it is, and then decides what response to make. The generation of the in interrupt is different from the out interrupt. The in interrupt is generated after the in buffer changes from empty to full, and the generation of the in interrupt requires the firmware to write to the in buffer. In other words, it is the operation of writing to the in buffer that triggers the generation of the in interrupt, not the generation of the in interrupt that triggers the operation of writing to the buffer. When the firmware detects the in interrupt, it also needs to clear the interrupt by reading the endpoint status register of the in endpoint.

2.3 Device response request
When the chip works in device controller mode, the work of the device side is to passively execute the request sent by the host. The request type is determined by reading the setup packet in the out buffer. A setup packet (i.e. request packet) has 8 bytes, and the request type can be determined based on the second byte. As can be seen from the flowchart, during the enumeration process, the host must issue requests to obtain descriptors, set addresses, set configurations, etc. For requests to obtain descriptors, it is necessary to further determine what kind of descriptor is being requested, which can be determined by the values ​​of the third and fourth bytes of the request. Once the request type is determined, the device can determine how to respond to the request. After determining what kind of descriptor the host has sent a request to obtain, the firmware writes the value of the corresponding descriptor to the endpoint buffer of the in endpoint. The method of writing the in endpoint buffer is similar to the register configuration.