65nm Virtex-5 FPGA process

The most important feature of the semiconductor industry is the continuous advancement of technology, which is upgraded every few years on average, driving down power consumption and costs, and improving performance. From 180nm to 130nm, and then to 90nm, 65nm and 45nm, these slightly boring numbers are accelerating our lives into the digital age filled with all kinds of electronic devices.

At the new process node, when programmable logic, logic devices, that is, CPLD and FPGA manufacturers bring back the honors jointly brought by electronic design industry experts and the electronic community to their headquarters again and again in the 65nm field in the near future, we have to think again about what kind of changes 65nm has brought to this industry, and why programmable logic solutions have continuously become the hot spot of the industry from the previous supporting role.

As we all know, many markets such as communications, instruments, industry, military industry, aerospace, etc. are characterized by small batches and multiple varieties. If a lot of resources are invested in developing a dedicated chip, it is very uneconomical. In addition, more and more companies realize that differentiated fast and flexible production is the way to survive and develop, but the high cost of chip design and manufacturing has hindered technological innovation. Fortunately, there are FPGAs. Engineers can use FPGAs to implement the required functions and algorithms, so that they do not have to be limited to a certain product or a certain manufacturer, but only to their creative thinking.

In order to compete with other types of devices, FPGA must meet the requirements of low cost, low power consumption, and high performance. The most direct and effective way is to adopt advanced technology. At the same time, since FPGA chips are a one-time R&D investment, they can be repeatedly used through software programming, allowing many customers to share the R&D costs. Therefore, FPGA manufacturers have spared no effort in adopting advanced technology. From 130nm, 90nm to 65nm, every advancement of new process technology is inseparable from their presence.

For example, Xilinx's 65nm Virtex-5, as the first 65nm device launched in the programmable field and the only one currently in mass production, is quite representative. Xilinx, which claims "Innovation in the Heart", uses advanced 3-layer oxide layer technology with different thicknesses on the new 65nm Virtex-5 to reduce leakage and static electricity, achieves lower dynamic power consumption and improves performance through 1.0V core voltage and strained silicon technology, uses 12-layer copper technology to reduce capacitor voltage, and uses nickel silicide automatic alignment technology to improve performance. In addition, Virtex-5 also uses ASMBL architecture and Express Fabric, and has built-in temperature and voltage sensors and other technologies. Compared with the previous generation 90nm FPGA, the speed is increased by an average of 30%, the capacity is increased by 65%, the dynamic power consumption is reduced by 35%, the static power consumption remains unchanged, and the chip area is reduced by 45%. Virtex-5 has a lookup table (LUT) with 6 independent inputs and a new diagonal interconnect structure, which reduces the logic level and improves the signal interconnection between building blocks, making the logic performance 30% higher than the previous generation Virtex-4 on average. Zou Zhixiong, senior marketing manager of Virtex solutions in Asia Pacific at Xilinx, revealed that the price of 65nm Virtex is expected to drop by 20% to 30% compared with 90nm devices.

Using the 6-input lookup table of the ExpressFabric architecture, only one logic unit is needed to implement a 64-bit distributed RAM, while the previous 4-input lookup table required 4 logic units.

System designers certainly like high performance, but they absolutely hate high power consumption. How to reduce power consumption without sacrificing speed and performance is also a big challenge. To reduce power consumption, manufacturers usually use lower core voltages, but the core voltage drop will sacrifice speed. For example, if the core voltage drops from 1.1V to 0.9V, the speed will drop by 17%. Zou Zhixiong explained that Virtex-5 has achieved a good balance between performance and power consumption by expanding the silicon molecule spacing, without increasing leakage current when using 1.0V voltage, and without sacrificing speed and performance.

High-speed signal processing and serial transmission

Mobile phones are digital, home appliances are smart, and high-definition TVs can be hung on the wall. The pure analog signal products we can find around us are becoming increasingly scarce. All products must be labeled with the word "digital" to be fashionable. The core of the digital world is to realize the processing of digital signals, including transformation, filtering, encoding and decoding, which can be achieved in many ways such as MCU, DSP, FPGA, hard-wired logic, etc. Hard-wired logic has the best processing efficiency, but the worst flexibility, and is very complex to develop. It can only adapt to one media format and fixed operations, and cannot meet the requirements of supporting multiple media formats. It has basically been eliminated. The strength of MCU is control, and its ability to process digital signals is limited. It can still cope with applications with limited data volume. As the name suggests, DSP is most suitable for digital signal processing, such as voice, video, and images, and the architecture of DSP is relatively simple, making it easy to increase the clock frequency. The performance of DSP is limited by many fixed hardware architectures, such as bus performance bottlenecks, a fixed number of multiplication and accumulation (MAC) modules, fixed memory, fixed hardware acceleration modules, and fixed data bandwidth. Therefore, this fixed hardware architecture of DSP is not suitable for many applications that require customized DSP function implementation. The biggest advantage of FPGA is parallel processing. It can handle a large number of different tasks at the same time. Therefore, when complex calculations are involved, some DSP tasks can be offloaded to FPGA for processing.

With the mutual penetration and compatibility of telecommunication networks, radio and television networks, and computer communication networks, and their gradual integration into a unified information communication network, the requirements for computing processing capabilities are becoming increasingly higher. At this time, it is difficult to rely solely on DSP. The DSP+FPGA method is often used to achieve system logic multiplexing and merging, realize new peripherals or bus interfaces, and accelerate performance in the signal processing chain.

The processing performance of FPGA itself is constantly improving, and it is likely to replace DSP in many applications, especially in some communication systems with evolving standards. FPGA can configure DSP segments to implement multiplexers, counters, multiplier accumulators, adders and many other functions, all without occupying logic structure resources. FPGA also has high on-chip memory bandwidth, large I/O bandwidth and high flexibility, which can provide high-performance programmable DSP functions at lower power consumption, while reducing system cost and board area. System designers can use one or several FPGAs to develop a circuit board that would have required dozens of DSPs and possibly multiple circuit boards. Because FPGA supports vertical migration within the same package, it is only necessary to replace devices of different specifications to implement low-end to high-end functions on the same circuit board design. Especially for multi-channel applications that process high-speed data, FPGA can achieve hundreds of floating-point multiplications per clock cycle, which is several times faster than the fastest DSP.

Taking Virtex-5 SXT FPGA as an example, the device's enhanced DSP logic slice (DSP48E) includes a 25x18-bit multiplier, a 48-bit second-level accumulation and arithmetic operation unit, and a 48-bit output that can be expanded to 96 bits. Wider data paths and outputs can support a wider dynamic range and higher precision, while also optimizing support for single-precision floating-point operations, while consuming only half the resources of a 90nm FPGA. The DSP48E logic slice also includes integrated hierarchical routing, supports parallel processing at full speed of 550MHz, and provides 352GMAC processing power using 640 DSP48E blocks. Other features include an independent C register and an extended second level that supports SIMD operations and pattern detection, enabling more efficient DSP implementation. Virtex-5's DSP48E logic slice can implement a variety of accelerated algorithms, achieve a higher degree of integration of DSP functions, and consume less power than previous Virtex devices.

FPGA also has a feature that MCU and DSP do not have, that is, high-speed hardware encryption function. Since FPGA is a parallel architecture, many bits of data can be encrypted at the same time. Virtex-5 supports AES encryption, and the software-based bitstream encryption and on-chip bitstream decryption logic use dedicated memory to store 256-bit encryption keys.

ML506 Entry-level DSP Development Board

Currently, serial communication is a hot topic in the electronics industry. This is mainly because serial communication can avoid the problem of crosstalk between signals in parallel communication and can achieve very high communication rates. For example, the transfer rate of SATA 2 is as high as 300MB/s, and the speed of PCI Express 2.0 can reach 500MB/s.

The advanced 65nm process enables faster switching speeds for transistors, thus supporting higher transmission rates. The SXT platform in the Virtex-5 series has 16 low-power 3.2Gbps RocketIO serial transceivers that support standard protocols such as CPRI/OBSAI, HD/SDI, Serial RapidIO, PCI Express, and Gigabit Ethernet. Built-in protocol modules and interfaces directly support PCI Express and Gigabit Ethernet.

Virtex-5 LXT FPGA integrates serial transceivers, built-in PCI Express endpoint modules and Ethernet media access controller modules. The PCI Express port has passed the PCI SIG V1.1 test. Virtex-5 transceivers have advanced transmission and reception equalization performance, as well as pre-emphasis, adaptive jitter and other functions, which can achieve excellent signal integrity and maximize the opening of the eye diagram. Users can also use development and debugging tools, design kits, IP, feature reports, etc. to quickly build standard-compliant serial interfaces.

Shifting business and technology development paradigms

When the 90nm process was widely used in 2005, many companies announced that they would use the 90nm process for mass production of their products. These companies included Intel, AMD, TI, NXP, Freescale, IBM, ATI, NEC, Samsung and Xilinx. Now, only Intel, AMD, IBM, Samsung, Nvidia and Xilinx have announced that they will use the 65nm process for mass production.

Although people are keen to talk about the issue of process size, the number of 65nm chip designs actually put into production is far less than expected. The reason is simple: it is not cost-effective. Although each process upgrade can reduce the manufacturing cost of wafers by half, it will increase the development cost of chips by 2, 3 or even more, and it is increasing exponentially. For example, the mold opening fee for 65nm chips is as high as 4 million US dollars, while the mold opening fee for 45nm chips will reach 9 million US dollars. Compared with the mold opening fee, the R&D cost of more advanced processes will be even more staggering. Designing a 45nm chip may cost 200 to 500 million US dollars. Not to mention ASIC manufacturers, even ASSP manufacturers may not be able to afford this huge expense. This is also the reason why joint design and joint R&D in the semiconductor industry are increasing. Only those chip companies that can share costs among many customers and designs can afford the increasingly expensive chip manufacturing and design costs. It is foreseeable that in the future, the list of manufacturers using 45nm, 32nm or even 22nm will only become shorter and shorter, and IC design with the most advanced process can only be a rivalry between a few big guys.

This is an advantage for FPGA manufacturers. Zou Zhixiong explained that programmable devices, due to their process characteristics and business model, actually let many customers and FPGA manufacturers share these huge R&D costs. For example, Xilinx has more than 20,000 customers, and everyone shares the $200 million cost of 45nm. In this way, each company actually only needs to bear $10,000, which undoubtedly shares the risk. The fabless foundry model was first initiated by Xilinx. This business model of sharing technical risks has made the development prospects of FPGA extremely broad.

In some markets with extremely high shipment volumes, 65nm FPGAs have no cost advantage over 90nm and 130nm ASIC/ASSP chips. If the FPGA process can be lower than 32nm, the old process ASIC/ASSP chips will lose out in terms of cost. Considering the risks and costs of chip development, as well as the uncertainty of the future market, the design of ASIC/ASSP will gradually decrease, and system manufacturers must turn to FPGAs to complete the design. Some traditional IC design industries may also give way to FPGA-based system design.

Currently, programmable solution providers are actively working with foundry partners to develop 45nm FPGAs, and 32nm and 22nm FPGAs are also in the works. Future FPGAs can also integrate other devices such as flash memory and embedded processors to achieve mixed processes and mixed voltages, turning FPGAs into a "virtual motherboard" where engineers can directly design mixed signals. In other words, system manufacturers no longer have to wait for IC suppliers to design the required chips, they can completely implement complete system functions on FPGAs. The traditional electronic system development model may be completely overturned under the push of FPGAs with ever-improving processes.

Mass production is a symbol of confidence

Since the launch of the 65nm Virtex-5 FPGA platform on May 15, 2006, Xilinx has released 13 devices based on three platforms (LX, LXT and SXT). Two of them, LX50 and LX50T, are currently available in volume production, and other models will soon enter volume production.

In the one year from the launch of samples to mass production, Xilinx has done a lot of work in high and low temperature testing, ESD protection, development tools, reference design, etc. Zou Zhixiong emphasized: "Mass production of FPGA means that customers can now safely use 65nm FPGA in large quantities for whole machine product manufacturing. Strict internal process control and close cooperation with foundry partners have achieved a satisfactory yield rate of 65nm process." In order to make it easier and faster for application design engineers to develop designs based on Virtex-5, Xilinx has optimized the software and overall solutions, providing free design tools, protocol development kits optimized for applications, general development boards and reference designs.

In addition, Xilinx adopts a dual foundry strategy to ensure supply stability. Both UMC and Toshiba have passed strict certification processes and NPI (new product introduction) evaluations. NPI evaluations include process evaluation (defect density, line yield, cycle, and key elements of mass production, etc.), verification and feature evaluation, mass production cooperation certification evaluation (content department mass production qualification certification results and mass production plan), packaging/assembly evaluation, final measurement yield and fault coverage evaluation, and logistics and product plan evaluation, etc., which lays a good foundation for smooth mass production. The dual foundry strategy also helps to achieve capacity expansion. When a foundry encounters a capacity bottleneck, the surplus capacity of another foundry can be used to meet market demand. The potential risk of dual foundries is that the processes of the two foundries will not be completely consistent, but this can be solved through rigorous testing and verification to ensure that the performance parameters of the final product received by the customer are within the tolerance range.

"Timing is business opportunity." Xilinx, which has been ahead of its closest competitor by a year and a half in terms of mass production, is attracting high-end supporters who are committed to differentiation and industry leadership with its "unique" momentum. At the same time, for customers who adopt 65nm solutions, it also means that customers can have more profits and greater chances of success. You know, seizing the market one year in advance may completely eliminate latecomers.