Design of DDS Excitation Constant Current Source Based on FPGA

At present, the signal generation part of the excitation power supply usually adopts direct frequency synthesis technology. The main functional circuit is composed of a voltage-controlled oscillator (VCO), a frequency multiplier, a frequency divider, a mixer and a filter. The entire system adopts open-loop control, that is, input set value → frequency synthesis → power amplification → output excitation current. This structure brings the following shortcomings to the excitation power supply: (1) Due to the use of an external voltage-controlled oscillator, the frequency range of the excitation signal is limited, generally about 50 kHz. (2) The system uses open-loop control, and the system accuracy depends on the accuracy and stability of each component, which makes the amplitude accuracy and stability of the excitation current poor, and the instrument has weak anti-interference ability. (3) Using direct frequency synthesis technology, there are a large number of analog circuits in the system, resulting in a large system size, heavy weight, high power consumption and poor reliability.

With the development of information technology, magnetic materials are widely used in the fields of communication, electricity, information, transportation, etc. The hysteresis loop is one of the important magnetic parameters of magnetic materials and is the essential characteristic of ferromagnetic materials. It is usually used in calculations and research related to magnetic materials and has important guiding significance for industrial production and scientific research.

This paper proposes a DDS signal generator based on FPGA. The signal generation circuit adopts direct digital frequency synthesis technology, namely DDS (Direct Digital Frequency Synth-esis). It is a new frequency synthesis technology that uses full digital technology and starts from the phase concept to directly synthesize the required waveform. It introduces advanced digital processing technology and methods into the field of signal synthesis, converts a series of digital signals into analog signals through a digital/analog converter, and performs frequency synthesis in the time domain. The main advantages of direct digital frequency synthesizers are: the output signal frequency is relatively wide relative to the bandwidth; the frequency resolution is good and the conversion time is fast; the phase remains continuous when the frequency changes; the integration is high, the volume is small, and the control is convenient. The entire signal source system adopts digital closed-loop control. By controlling the instantaneous value of the excitation current through PID closed-loop control, the excitation current can instantaneously track the given amplitude, accelerate the dynamic response of the system, and improve the adaptability to nonlinear loads. Compared with traditional signal sources, it can better meet the needs of magnetic test equipment.

1 Working Principle of DDS

The working principle of DDS is shown in Figure 1. The main basic components are: phase accumulator; phase-amplitude converter, that is, sine lookup table ROM; D/A converter and appropriate filters. The phase accumulator is the core of the DDS system. It consists of an adder and a phase register. Under the action of the reference clock, the phase accumulator accumulates continuously according to the frequency control word as the step size, and the accumulated result is transmitted to the sine lookup table ROM in an incremental manner. The sine lookup table stores the digital amplitude information corresponding to a period of sine wave at each phase point. Since the output of the phase accumulator is connected to the address line of the waveform memory (ROM), the change of its output is equivalent to a lookup table. In this way, the waveform sampling value stored in the waveform memory can be found through the lookup table and then sent to the D/A converter, which generates a series of voltage steps with the clock pulse as the sampling rate. The filter further smoothes the sawtooth step wave output by the D/A converter, which is close to the sine wave, and attenuates unnecessary stray signals to make the output the required smooth waveform.

Due to the limitation of the phase accumulator word length, when the phase accumulator accumulates to a certain value, its output will overflow, so the address of the waveform memory will cycle once, which means that the output waveform cycles once. Therefore, when the frequency word takes different values, the overflow time of the phase accumulator can be changed, thereby changing the output frequency under the condition that the clock frequency remains unchanged.

Assume the frequency control word is K, the system reference clock is fc, the number of bits of the phase accumulator is N, and the output frequency is fo, then the relationship between input and output can be obtained as follows:

When K=1, the frequency resolution of DDS can be obtained

2 Hardware design of excitation constant current source

The excitation signal generator circuit system is mainly composed of FPGA-based DDS circuit, MCU control circuit, DAC circuit, low-pass filter (LPF), human-machine interface, system clock and system power supply. The system block diagram is shown in Figure 2.

2.1 FPGA-based DDS circuit

2.1.1 Phase Accumulator

For designing DDS signal source using FPGA, the phase accumulator is a key part that determines the performance of DDS circuit. The phase accumulator is composed of N-bit accumulator and N-bit register cascaded. For each clock pulse, the phase register samples the sum of the value of the phase accumulator in the previous clock cycle and the frequency control word K, and uses it as the output of the phase accumulator in this clock cycle. As can be seen from formula (2), the larger the number of bits N of the phase accumulator, the smaller the frequency resolution obtained, but at a higher operating frequency, a larger delay will be generated and the speed requirement cannot be met. In timing circuits, pipeline technology is usually used to increase the speed, but the cost is to increase the number of registers and occupy more FPGA data. After comprehensive consideration, a 32-bit accumulator and a four-stage pipeline structure are used.

2.1.2 Phase-Amplitude Converter

The phase-amplitude converter is composed of ROM, which converts the digital phase information of the output of the phase accumulator into a sine wave value. In FPGA, ROM is generally implemented by EAB, and the size of the ROM table increases exponentially with the number of address bits or data bits. Therefore, the design of the phase-amplitude converter is another key factor affecting the performance of DDS. Under the premise of meeting the signal design index requirements, it mainly depends on reducing resource overhead. Considering that this design only needs to output a sine signal, the sine wave signal is odd-symmetrical about the point (π, 0), and only 1/2 cycle of waveform data needs to be stored. In addition, according to the fact that the waveform is even-symmetrical about the straight line x=π/2 in the left half cycle, only 1/4 cycle of sine function value needs to be stored. The entire sine code table can be obtained through appropriate transformation, which can save 3/4 of the resources. [page]

2.2 Low-pass filter module

DDS has an obvious disadvantage, that is, the closer the output frequency is to the high end of the Nyquist bandwidth, the fewer the sampling points, and the greater the spurious interference of its output. The output waveform has a large number of harmonic components and system clock interference. In order to obtain the signal within the required frequency band, it is necessary to add a filter to the output end of the DDS to achieve it. The low-pass filter can better filter out clutter and smooth the signal, so the design of the low-pass filter is particularly important. The quality of the filtering characteristics has an important impact on the performance of the output signal.

In order to achieve better filtering effect, the filter adopts a segmented filtering method consisting of four-to-one analog switches and precision operational amplifiers: a Butterworth active low-pass filter is used, the amplitude of which is very flat in the passband, the filtering circuit is a second-order Butterworth low-pass filter circuit, and the selection of the filter frequency band parameters is achieved by controlling the analog switch by the control signals nINH, S0, and S1 output by the FPGA.

2.3 Amplitude Control

The amplitude control circuit of this design adopts a digital control method to adjust the DAC reference voltage. It uses two D/A cascades. The digital-to-analog converter DAC2 uses an external variable reference source. By changing the value of the reference source, the full amplitude current value of the output is changed. The variable reference source is generated by DAC1. The reference voltage of DAC1 is provided by a precision voltage reference chip with an output voltage of 1.25 V. If the amplitude output word of DAC1 is N1, the reference voltage of DAC1 is

Assume that the digital input word of DAC2 is N2, then the output voltage after current/voltage conversion is

2.4 Human-Computer Interaction

In order to conveniently and quickly control the frequency word input and amplitude control of DDS, this design uses a single-chip microcomputer to realize the control of the DDS signal generator. The frequency word and amplitude data word of DDS have more bits, while the output port of the single-chip microcomputer has limited bits, so the communication between the single-chip microcomputer and the FPGA adopts the SPI (Serial Peripheral Interface) method, and the single-chip microcomputer transmits the control command word to the FPGA. At the same time, in order to facilitate input control, a keyboard and display system are added.

3 Implementation of digital closed-loop control system

The designed excitation constant current source mainly provides excitation power for magnetic measuring instruments, so its accuracy and stability are required to be high. A current control strategy is used for closed-loop control, and the structural block diagram is shown in Figure 3. When adjusting the excitation current amplitude, the excitation current is first sampled for multiple cycles, and then its effective value is calculated and compared with the input set value. If the error ε is outside the allowable range, a new control quantity is obtained through the incremental PID algorithm in the single-chip microcomputer according to the actual error situation, and then transmitted to the FPGA control amplitude adjustment. The high-frequency components are filtered out by a low-pass filter, and then amplified by power to obtain a high-precision excitation current.

4 System Simulation and Verification Analysis

The compilation was completed in Altera's QuartusⅡ environment, using a top-down design method, that is, starting from the overall system requirements, the design content was refined, and finally the overall design of the system hardware was completed. After completing the DDS design, the simulation was performed in Modelsim by writing Testbench. In QuartusⅡ, the output signal frequency was set to 1 MHz, and after 50 μs, it was changed to 500 kHz for simulation. The simulation results are shown in Figure 4. The simulation data generated in Modelsim was verified to be completely correct and met the design requirements.

When testing the hardware system of the excitation signal source, first complete the system hardware connection, load the program, set the output signal frequency to 1 MHz, and measure the actual output waveform with the oscilloscope as shown in Figure 5. The results of simulation in the Modelsim environment and testing on the hardware platform show that the excitation signal source can obtain a better setting waveform and can be applied to the testing of magnetic materials.

5 Conclusion

运用Verilog硬件编程语言结合DDS技术，利用FPGA器件强大的硬件功能，提高了系统集成度，实现了输出信号相对带宽宽、稳定性好；其相位累加器在一定系统时钟和累加器位宽条件，输出信号分辨率越小，频率控制字的传输时间以及器件响应时间都很短，使输出信号频率切换时间较短，可以达到ns级，且频率变化时，相位保持连续，系统采用闭环控制，励磁电流输出精度高，调节速度快。对磁性材料测量仪所要求的励磁信号源而言，本设计不但满足所有技术指标，而且集成度高、体积小、显著地降低了成本。