DS1307 interfaces with 8051-compatible microcontrollers

This application note provides information on how to interface the DS1307 real-time clock (RTC) to a microcontroller and provides some example code to access the device.

introduce

The DS1307 serial real-time clock integrates a 2-wire serial interface and can be controlled using an 8051-compatible microcontroller. The DS1307 in this example is connected directly to two I/O ports on the DS5000 microcontroller, and the 2-wire handshaking is handled by low-level drivers, which is discussed in this application note.

DS1307 Description

The DS1307 serial real-time clock is a low-power, full BCD clock/calendar plus 56 bytes of non-volatile SRAM. Address and data are transferred serially over a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day of the week, date, month and year information. For months with fewer than 31 days, the end of the month is automatically adjusted, including corrections for leap years. Clock operates in 24-hour or 12-hour format with AM/PM indicator. DS1307 has a built-in power detection circuit that can detect power failure and automatically switch to battery power.

DS1307 working principle

The DS1307 operates as a slave device on the serial bus. Access is obtained by implementing the START condition and providing the device identification code followed by the register address. Subsequent registers can be accessed sequentially until a STOP condition is executed. Start and stop conditions are generated using the low-level drivers, SEND_START and SEND_STOP, in the included DS5000 code. In addition, the subroutines SEND_BYTE and READ_BYTE provide the 1307-line handshake required to write and read 8-bit words between DS2.

Hardware Configuration

The system configuration is shown in Figure 1. The DS1307's 2-wire bus connects to the DS5000's two I/O port pins: SCL - P1.0, SDA - P1.1. The DD voltage of the fifth generation is 5V, RP= 5KΩ, and the DS5000 uses a 12 MHz crystal. The other peripheral can be any other device that recognizes the 2-wire protocol, such as the DS1621 digital thermometer and thermostat. Interfacing to the D5000 is accomplished using the DS5000T suite of hardware and software. This development kit allows the PC to be used as a dumb terminal, using the DS5000's serial port to communicate with the keyboard and monitor.

Figure 1. Typical 2-wire bus configuration.

The following bus protocols are defined (see Figure 2).

During data transmission, as long as the clock line is high, the data line must remain stable. Changes on the data line while the clock line is high will be interpreted as a control signal.

Therefore, the following bus conditions are defined:

Start data transfer: When the clock line is high, the change in the state of the data line from high to low defines the START condition.

Stop data transfer: When the clock line is high, the change in the state of the data line from low to high defines a STOP condition.

Data Valid: The state of the data line indicates valid data when the data line remains stable during the high period of the clock signal after the START condition. The data on the line must change during the low period of the clock signal. There is one clock pulse for each data bit.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is unlimited and is determined by the master device. Information is transmitted in bytes and each receiver acknowledges it with the ninth bit.

Acknowledgment: Each receiving device, when addressed, must generate an acknowledgment after each byte received. The master device must generate additional clock pulses associated with this acknowledge bit.

The asserted device must pull down the SDA line during the acknowledge clock pulse so that the SDA line settles low during the high period of the asserted associated clock pulse. Of course, setup and hold times must be considered. The master must signal the end of data to the slave by generating an acknowledge bit on the last byte output from the slave. In this case, the slave must hold the data line high to enable the master to generate a STOP condition.

Figure 2 details how data transfer is accomplished on a 2-wire bus. Depending on the state of the R/W bit, two types of data transfers are possible:

Data transfer from master transmitter to slave receiver. The first byte transmitted by the master is the slave address. Next are some data bytes. The slave returns an acknowledge bit after each received byte. Data is transmitted using the most significant bit (MSB) first.

Data transfer from slave transmitter to master receiver. The first byte (slave address) is transmitted by the master. The slave then returns an acknowledge bit. What follows is the transfer of multiple data bytes from the slave. The master returns an acknowledge bit after all received bytes except the last one. At the end of the last received byte, a non-acknowledgement is returned.

Figure 2. Data transfer on a 2-wire serial bus.

The master device generates all serial clock pulses and start and stop conditions. The transfer ends with a "stop" condition or a repeated "start" condition. Since a repeated START condition is also the start of the next serial transfer, the bus is not released. Data is transmitted using the most significant bit (MSB) first.

DS1307 can work in the following two modes:

Slave Receive Mode (DS1307 Write Mode): Serial data and clock are received via SDA and SCL. After each byte is received, an acknowledge bit is sent. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after receiving the slave address and direction bits (see Figure 3). The address byte is the first byte received by the master after generating the start condition. The address byte contains the 7-bit DS1307 address, which is 1101000, followed by the direction bit (R//W), which is 0 for writes. After receiving and decoding the address byte, the DS1307 outputs an acknowledge on the SDA line. After DS1307 confirms the slave address + write bit, the host sends the register address to DS1307. This will set the register pointer on the DS1307. The host then begins sending each byte of data, and the DS1307 acknowledges each byte received. The master will generate a stop condition to terminate data writing.

Slave Transmitter Mode (DS1307 Read Mode): The first byte is received and processed in the same way as Slave Receiver mode. However, in this mode, the direction bit will indicate the opposite direction of transfer. Serial data is transmitted on SDA by the DS1307, while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see Figure 4). The address byte is the first byte received by the master after generating the start condition. The address byte contains the 7-bit DS1307 address, which is 1101000, followed by the direction bit (R/W), which is 1 when read. After receiving and decoding the address bytes, the DS1307 enters an acknowledgment on the SDA line. The DS1307 then sends data starting at the register address pointed to by the register pointer. If the register pointer is not written before read mode is initiated, the first address read is the last address stored in the register pointer. The DS1307 must send a non-acknowledge bit from the master to terminate the read operation.

Figure 4. Data reading—slave-to-transmitter mode.

Software operation

DS5000 interface

The software in Appendix 1 is used to connect the DS1307 to the DS2 via the 5000 line interface. The DS5000 is programmed using Dallas Semiconductor's DS5000T evaluation board, which allows the PC to be used as a dumb terminal. The KIT5000K software environment included with the DS5T evaluation kit provides a high-level interface for loading application software into the DS5000 or setting its configuration parameters through program commands. The KIT5K software includes a dumb terminal emulator that allows users to run application software in the DS5000 and communicate with the user through the PC COM port.

DS1307 source code

The first part of the code in the appendix is ​​used to configure the DS5000 for serial communication with the PC. Also at the beginning of the code is the MASTER_CONTROLLER subroutine for controlling the demo software.

The subroutine immediately following the MASTER_CONTROLLER subroutine is used to control the low-level drivers of the 2-wire interface. They are not specific to the DS1307 but will work with any 2-wire compatible slave device. These subroutines are:

SEND_START

This subroutine is used to generate a start condition on the 2-wire bus.

SEND_STOP

This subroutine is used to generate a Stop condition on a 2-wire bus.

SEND_BYTE

This subroutine sends a 2-bit MSB word over the 8-wire bus, with a priority of 9,000 acknowledgment pulses.

READ_BYTE

This subroutine reads a 2-bit word over the 8-wire bus. It checks the LASTREAD flag to clear, indicating when the last read from the slave device was made. If it is not the last read, the DS5000 clocks in at 9K, if this is the last read from the slave, the DS5000 sends "Unacknowledged".

SCL_HIGH

This subroutine transitions the SCL line from low to high and ensures that the SCL line is high before continuing.

Delay and DELAY_4

These two subroutines are included to ensure that the 2-wire bus timing is maintained.

The remaining code in the appendix is ​​dedicated to demonstrating the capabilities of the DS1307. Demonstrated features include:

Set time

The time is read from the keyboard and stored in the DS5000 scratchpad memory. It is then transmitted to the DS1307 via a 2-wire interface.

Set up memory

Read in a single hexadecimal byte from the keyboard and write to the entire user RAM of the DS1307.

Read date/time

The date and time are read over the 2-wire bus and stored in the DS5000 scratchpad memory. Then write it to the screen. This continues until a key on the keyboard is pressed.