DS1245Y/AB
DS1245Y/AB
1024K Nonvolatile SRAM
FEATURES
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
•
10 years minimum data retention in the absence of
external power
•
Data is automatically protected during power loss
•
DIP–package devices directly replace 128K x 8 vola-
tile static RAM
•
Unlimited write cycles
•
Low-power CMOS
•
Read and write access times as fast as 70 ns
•
Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first
time.
•
Full +10% V
CC
operating range (DS1245Y)
•
Optional +5% V
CC
operating range (DS1245AB)
•
Optional
industrial temperature range of -40
o
C to
+85
o
C, designated IND
•
JEDEC standard 32–pin DIP package
•
Low Profile Module (LPM) package
– Fits into standard 68–pin PLCC surface–mount-
able sockets
– 250 mil package height
NC
A15
A16
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
32-PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
PIN DESCRIPTION
A0 - A16
DQ0 - DQ7
CE
WE
OE
V
CC
GND
NC
-
-
-
-
-
-
-
-
Address Inputs
Data In/Data Out
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
No Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34–PIN LOW PROFILE MODULE (LPM)
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
100495 1/10
DS1245Y/AB
DESCRIPTION
The DS1245 1024K Nonvolatile SRAMs are
1,048,576-bit, fully static, nonvolatile SRAMs organized
as 131,072 words by 8 bits. Each NV SRAM has a self-
contained lithium energy source and control circuitry
which constantly monitors V
CC
for an out-of-tolerance
condition. When such a condition occurs, the lithium en-
ergy source is automatically switched on and write pro-
tection is unconditionally enabled to prevent data cor-
ruption. DIP-package DS1245 devices can be used in
place of existing 128K x 8 static RAM directly conform-
ing to the popular bytewide 32-pin DIP standard.
DS1245 devices in the Low Profile Module package are
specifically designed for surface mount applications.
There is no limit on the number of write cycles which can
be executed and no additional support circuitry is re-
quired for microprocessor interfacing.
is terminated by the earlier rising edge of CE or WE. All
address inputs must be kept valid throughout the write
cycle. WE must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initi-
ated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. How-
ever, if the output drivers are enabled (CE and OE ac-
tive) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1245AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1245Y provides full functional capability
for V
CC
greater than 4.5V and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below ap-
proximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power-up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
4.75 volts for the DS1245AB and 4.5 volts for the
DS1245Y.
READ MODE
The DS1245 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 17 address inputs (A
0
-
A
16
) defines which of the 131,072 bytes of data is ac-
cessed. Valid data will be available to the eight data out-
put drivers within t
ACC
(Access Time) after the last ad-
dress input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be mea-
sured from the later occurring signal (CE or OE) and the
limiting parameter is either t
CO
for CE or t
OE
for OE rath-
er than address access.
FRESHNESS SEAL
Each DS1245 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than V
TP
, the lithium energy
source is enabled for battery backup operation.
WRITE MODE
The DS1245 devices excute a write cycle whenever the
WE and CE signals are active (low) after address inputs
are stable. The later occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle
100495 2/10
京公网安备 11010802033920号
EEWORLD
