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This board is based on the standard 6U VPX architecture and is a general high-performance signal processing platform independently developed by our company. The board uses a TI DSP TMS320C6678 and a Xilinx Virtex 7 series FPGA XC7V690T-2FFG1761I as the main processor, and Xilinx's Aritex XC7A200T as the auxiliary processor. XC7A200T is responsible for managing the power-on timing, clock configuration, system and module reset, program reconfiguration, etc. of the board. It provides you with rich computing resources. As shown in Figure 1:
Signal processing platform block diagram
2. Design reference standards
- ● VITA46.0 VPX Base Standard
- ● VITA46.3 Serial RapidIO on VPX Fabric Connector
- ● VITA46.4 PCI Express on VPX Fabric Connector
- ● VITA46.7 Ethernet on VPX Fabric Connector
- ● DSP plugs in a cluster of DDR3, data width 64bit, capacity 2GB;data rate 1333MHz;
- ● DSP external NorFlash capacity 32MB;
- ● DSP adopts EMIF16-NorFlash loading mode;
- ● DSP connects one 1000BASE-T Gigabit Ethernet to the front panel;
- ● DSP connects one 1000BASE-T Gigabit Ethernet to VPX P4;
- ● DSP connects PCIe x2 to VPX P2;
- ● Two DDR3 clusters are plugged into FPGA, each with 4GB capacity, 64bit bit width, and a total capacity of 8GB; data rate is 1600MHz;
- ● FPGA external NorFlash capacity 128MB;
- ● The loading mode of FPGA is BPI mode;
- ● FPGA is connected to 2 FMC-HPCs;
- ● FPGA connects GTH x8 to VPX P1;
- ● FPGA connects GTH x4 to VPX P2;
- ● FPGA connects one QSFP+ to the front panel; optical port rate 40Gbps;
- ● DSP and FPGA are interconnected via SRIO x4 @ 5.0Gbps/per Lnae;
- ● DSP and FPGA realize GPIO and SPI interconnection;
- ● DSP and CFPGA realize GPIO, SPI, and EMIF interconnection;
- ● FPGA and CFPGA realize GPIO interconnection;
- ● CFPGA connects a 1000BASE-T Gigabit Ethernet to VPX P4.
- ● The board requires industrial-grade chips and the structure meets earthquake resistance requirements.
4. Physical properties
● Operating temperature: Commercial grade 0℃ ~ +55℃, industrial grade -40℃~+85℃●Operating humidity: 10%～80%
● Single power supply, whole board power consumption: 40W
● Voltage: DC +12V, 5A
● Ripple: ≤10%
Signal processing, radio communications field.
7. Integrated application of collection, storage and computing
This application mode uses the VPX expansion backplane to access four-way M.2 solid-state hard drive storage.
Each storage disk uses a PCIE3.0 x4 interface with the FPGA to give full play to the performance of a single storage disk. For example, if the continuous read and write bandwidth of a single disk is ≥2GB/s, then the continuous read and write bandwidth of the storage array of a single disk is ≥2GB/s; when multiple disks work in parallel, the read and write bandwidth of the storage array increases exponentially, ≥4GB/s for 2 disks, ≥8GB/s for 4 disks, and so on.
The storage capacity of the storage array is determined by the configuration of a single disk. Currently, the storage capacity of a single NVME storage disk can be 512GB, 1TB, 2TB, 4TB, 8TB, and 16TB. For example, if 4 storage disks are configured, the storage array capacity can reach up to 64TB.
The hard disk is managed through the file system. The FPGA's PCIeX4 is interconnected with the 6U VPX motherboard. The operating system directly maps and manages the hard disk, and can also be exported to other server devices through the front panel QSFP+ optical fiber.
FMC daughter card can expand high-speed AD, DA, and can also expand 8-channel optical fiber, image daughter card, etc.
The advantage of this solution is that it integrates collection, storage, and calculation, reduces hardware costs, power consumption, and reduces the size and weight of the equipment. The problem is that the FPGA program is highly integrated and difficult to develop.
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千斤顶
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