s3C2440 Memory controller

Hardware Design

The first is the selection of BANK0. If you choose to connect BANK0 to NAND Flash, you need to set the status of pins OM1 and OM0 to 0, which means it is NAND FLASH mode. . NANDFlash mode will automatically

The first 4MB of NANDFLASH content is copied to memory.

Secondly, the pins of S3C2440 SDRAM are as follows:

nSRAS: SDRAM row select pin　

nSCAS: SDRAM column select pin

nSCS: chip select signal

DQM[3:0]: Mask is to mask unnecessary bits. For example, if a 32-bit chip connected needs to write 8-bit data, then the other bits will be masked.

SCLK: clock

SCKE: clock enable

nBE[3:0]: DATA mask. Because SDRAM can only extract 8 bits of data from the core at a time, this DQM is used to distinguish the upper eight bits and the eighth bit when the user selects 32-bit and 16-bit data. Generally connected to the LDQM and HDQM of SDRAM. LDQM connects to DQM0 HDQM connects to DQM1 (only for 16bit SRAM)

nWBE: Write Byte Enable

Among them, nBE, nWBE, and DQM share a pin array and their relationship is as follows:

If ROM is connected, nWBE needs to be connected to the nWE pin of the chip. byte enable

If you want to connect SRAM, nWE is connected to the nWE pin on the chip. UB and LB on the SRAM are connected to BE0 and BE1 respectively.

If connected to SDRAM, DQM0 needs to be connected to the LDQM on the chip and DQM1 needs to be connected to UDQM.

See the chip manual below:

1. CLK is connected to the SDRAM CLK of the chip

2. CKE: Clock enable

3. BA0 and BA1 form a selector that can select four BANKs (0,1,2,3) in SDRAM.

5 CS: Film Selection

6. CAS: column address selection

7. RAS: Row address selection

8. WE: Write enable

9. LDQM and UDQM masks. .

sequential operations

Determine the direction of the program and timing according to the manual:

1. The SDRAM we use is EM63A165TS 

2. Let’s look at BWSCON first: Since we set the SDRAM to bank 6, the registers we want to look at are:

ST6: Whether UB and LB are used? Because SDRAM only uses DQM instead of UB/LB, it is 0

WS6: Wait. Because waiting is not used, it is 0 (SDRAM has no waiting pin)

DW6: Bit width selection 16 bits   

3. Set BANKCON6. Since it is SDRAM, set MT to 11.

Tac: The time for address establishment before chip selection. Since HCLK is 100M, this bit can be set to 0.

cos can be set to 0 because the time is very short.

The last SCAN: Since the column in the manual is 9, 01 is selected.

4. Set refresh register:

22 and 23 bits are all 1 to refresh SDRAM

Trp manual is 21ns and HCLK is 100M (10ns) so it should be 01 3 clock cycles (10*3 >> 21ns)

Refresh frequency: The frequency in the manual is 8192. Refresh 64ms. Substitute into the formula Refresh period = (2^11-refresh_count+1)/HCLK

to 1267 

5 bank Size: Use burst mode with bit 7 set to 1

Bit 5: SDRAM can enter sleep state

The fourth bit: SCLK is only executed when entering SDRAM access

Position 2:0: Select 64M

6: MRSRB6: 0x20