2440 controller gleanings

To put it bluntly, the controller of 2440 can be understood as the FMSC in stm32, which is very similar.

A range of 1GB can be externally addressed. It is an intermediate bus device for communication between the CPU and external peripherals. 

For example, the network card SDRAM expansion serial port is connected to the CPU through this controller.

Start learning about SDRAM now

SDRAM we use EM63A165TS

1. NOR FLASH and NAND FLASH program startup methods

When using nor Flash: Address 0 points to the read instruction in nor flash.

When using nand flash: The first 4K code of nand flash will be copied to the internal 4k memory.

In 2440 bank 7 and bank 6 must be equal in size

The size of bank1 requires hardware (OM1 and OM2 pins to adjust the bit width) because it is connected to the boot pin.

BWSCON: Every four bits control a bank, the highest 4 bits correspond to bank7 

(1). STx: Set the data mask pin of the startup disable SDRAM. For SDRAM, this bit should be 0. For SRAM, it should be 1.

(2). WSx: Whether to use the storage Wait signal

(3) DWx: Use the bit width of the bank 

Here our SDRAM is connected to BANK6 (CS6)

Among them UB/LB means the upper 8 bits and the lower 8 bits

The starting address of Bank6 is 0x3000_000

BANKCONx:

Control the access timing of external devices BANK0~BANK5, use the default 0x0700 

Control BANK6~BANK7: (1) BANK MT ([15:16]) but when it is 00 it is SRAM and when it is 11 it is SDRAM

When set to 00, the subsequent settings are the same as those of Bank0~bank5.

When set to 01:

Trcd[3:2]: RAS to CAS delay The delay between rows and columns should be set to 1

SCAN [1:0]: The number of column address digits of SDRAM (this chip is 9 bits), so it is 01

REFRESH:

SDRAM must enable refresh function

22-bit: Auto refresh

Bit 21: 0

20:0

19:18: Default value 11

10:0: (2^11 - refresh_count+1)/HCLK

BANKSIZE: 

7: Burst transmission

6: Use SCKE to put SDRAM into power saving mode

4: Send SCLK signal only when accessing SDRAM

2:0: The size of bank6/7 can be changed, here it is 64MB

This is how to set it up 

program:

@**************************************************** ************************

@File:head.S

@ Function: Set SDRAM, copy the program to SDRAM, then jump to SDRAM to continue execution

@****************************************************** ************************     

.equ MEM_CTL_BASE, 0x48000000

.equ SDRAM_BASE, 0x30000000

.text

.global_start

_start:

    bl disable_watch_dog @ Turn off WATCHDOG, otherwise the CPU will keep restarting

    bl memsetup @ Set up storage controller

    bl copy_steppingstone_to_sdram @ Copy code to SDRAM

    ldr pc, =on_sdram @ Jump to SDRAM to continue execution

on_sdram:

    ldr sp, =0x34000000 @ Set the stack because the makefile initially points to 300000, and the first few lines occupy the stack (+4 for each instruction). . So the pointer here points to the address of main. The memory is 64MB, so it is the top of the stack 

    bl main

halt_loop:

    b halt_loop

disable_watch_dog:

    @ Just write 0 to WATCHDOG register

    mov r1, #0x53000000

    mov r2, #0x0

    str r2, [r1]

    mov pc, lr @ return

copy_steppingstone_to_sdram:

    @Copy all the 4K data of Steppingstone to SDRAM

    @Steppingstone The starting address is 0x00000000, and the starting address in SDRAM is 0x30000000

    mov r1, #0

    ldr r2, =SDRAM_BASE

    mov r3, #4*1024

1: 

    ldr r4, [r1],#4 @ Read 4 bytes of data from Steppingstone and add 4 to the source address

    str r4, [r2],#4 @ Copy this 4-byte data to SDRAM, and add 4 to the destination address

    cmp r1, r3 @ Determine whether it is completed: the source address is equal to the unused address of Steppingstone?

    bne 1b @ If copying is not completed, continue

    mov pc, lr @ return

memsetup:

    @ Set up the storage controller to use peripherals such as SDRAM

    mov r1, #MEM_CTL_BASE @ The starting address of the 13 registers of the storage controller

    adrl r2, mem_cfg_val @ the starting storage address of these 13 values

    add r3, r1, #52 @ 13*4 = 54

1: 

    ldr r4, [r2], #4 @ Read the setting value and add 4 to r2

    str r4, [r1], #4 @ Write this value to the register and add 4 to r1

    cmp r1, r3 @ Determine whether all 13 registers have been set

    bne 1b @ If not written, continue

    mov pc, lr @ return

.align 4

mem_cfg_val:

    @Storage the setting values ​​of 13 registers of the controller

    .long 0x22011110 @BWSCON

    .long 0x00000700 @BANKCON0

    .long 0x00000700@BANKCON1

    .long 0x00000700 @BANKCON2

    .long 0x00000700 @BANKCON3 

    .long 0x00000700@BANKCON4

    .long 0x00000700 @BANKCON5

    .long 0x00018005@BANKCON6

    .long 0x00018005@BANKCON7

    .long 0x008C07A3 @ REFRESH

    .long 0x000000B1@BANKSIZE

    .long 0x00000030 @MRSRB6

    .long 0x00000030 @MRSRB7