Things about S3C2440’s interrupts (1) Assembly explanation

1. There are 7 interrupt modes in ARM:

                                          1. User mode: used for daily program running

                                          2. Fast interrupt mode: Used for high-speed data transmission or channel processing. This mode has the highest priority and is most likely to be triggered. There are 32 interrupts and only one fast interrupt can be triggered.

                                          3. Interrupt mode: used for ordinary interrupt mode

                                          4. Management mode: Protection mode used by the operating system

                                          5. Data access termination mode: Enter this mode when data or instructions and reading are terminated

                                          6. System mode: Runs privileged operating system tasks

                                          7. Undefined instruction termination mode: Entering this mode when an undefined instruction is executed can be used to support hardware emulation.

2. First, look at the PSR (program status register)

     If the F-bit of this register is set to 1, the arm will no longer accept fast interrupt requests. In addition, if the I-bit is set to 1, the CPU will turn off all interrupts. 

The figure above explains the interrupt pattern except LCD:

SRCPND This register can query where an interrupt occurred.

SUBSRCPND This register is used to manage 11 secondary important interrupts such as the serial port.

SUBMASK is used to mask the interrupt provided by SUBSRCPND

MASK is used to mask the interrupt on the SRCPND register

MODE: When set to 1, this register can be set to fast interrupt mode

Priority is as shown below:

This figure illustrates that the priority is determined by these six arbiters. The combination of register bits ARB_Mode and ARB_SEL can achieve priority conversion as follows:

 The INTPND register records which interrupt has the highest priority and only one bit of this register can be set to 1.

Let’s analyze the code:

 1 @************************************************ ****************************

 2 @File:head.S

 3 @ Function: Initialization, setting the stack of interrupt mode and management mode, and setting the interrupt processing function

 4 @************************************************ ****************************       

 5    

 6. extern main

 7.text 

 8.global_start 

 9_start:

10 @************************************************ ****************************       

11 @ Interrupt vector, in this program, except for Reset and HandleIRQ, other exceptions are not used

12 @************************************************ ****************************       

13 b Reset

14 

15 @ 0x04: Vector address of undefined instruction abort mode

16 HandleUndef:

17 b HandleUndef 

18  

19 @ 0x08: Vector address of management mode, enter this mode through SWI instruction

20 HandleSWI:

21 b HandleSWI

twenty two 

23 @ 0x0c: Vector address of exception caused by instruction prefetch termination

24 HandlePrefetchAbort:

25 b HandlePrefetchAbort

26 

27 @ 0x10: Vector address of exception caused by data access termination

28 HandleDataAbort:

29 b HandleDataAbort

30 

31 @ 0x14: reserved

32 HandleNotUsed:

33 b HandleNotUsed

34 

35 @ 0x18: Vector address of interrupt mode

36 b HandleIRQ

37 

38 @ 0x1c: Vector address of fast interrupt mode

39 HandleFIQ:

40 b HandleFIQ

41 

42 Reset:                  

43 ldr sp, =4096 @ Set the stack pointer. The following are C functions. The stack needs to be set before calling.

44 bl disable_watch_dog @ Turn off WATCHDOG, otherwise the CPU will keep restarting

45     

46 msr cpsr_c, #0xd2 @ Enter interrupt mode

47 ldr sp, =3072 @ Set interrupt mode stack pointer

48 

49 msr cpsr_c, #0xd3 @ Enter management mode

50 ldr sp, =4096 @ Set the management mode stack pointer,

51 @ In fact, after reset, the CPU is in management mode.

52 @ The previous "ldr sp, =4096" completes the same function, this sentence can be omitted

53 

54 bl init_led @ Initialize the GPIO pin of the LED

55 bl init_irq @ Call the interrupt initialization function, in init.c

56 msr cpsr_c, #0x53 @ Set I-bit=0, enable IRQ interrupt

57     

58 ldr lr, =halt_loop @ Set return address

59 ldr pc, =main @ Call main function

60 halt_loop:

61 b halt_loop

62 

63 HandleIRQ:

64 sub lr, lr, #4 @ Calculate return address

65 stmdb sp!, { r0-r12,lr } @ Save the used registers

66 @ Note that the sp at this time is the sp in interrupt mode.

67 @ The initial value is 3072 set above

68     

69 ldr lr, =int_return @ Set the return address after calling the ISR or EINT_Handle function  

70 ldr pc, =EINT_Handle @ Call the interrupt service function, in interrupt.c

71 int_return:

72 ldmia sp!, { r0-r12,pc }^ @ Interrupt return, ^ means copy the value of spsr to cpsr

73     

Some notes:

Line 46: 

msr cpsr_c, #0xd2

msr means to store an immediate value into a PSR (program status register), then this register is cpsr_c, also known as register R16, which is a register that records status (please refer to 2440datasheet P72)

This is the R16 register. When setting the interrupt, the seventh and sixth bits need to be set to 1. This way, interrupts and fast interrupts are turned off at the beginning.

The last five bits are set to interrupt mode (see datasheet P78)

Line 47:

 ldr sp, =3072 @ Set interrupt mode stack pointer

What this actually involves is to allocate a memory area to the interrupt. This number can be chosen "arbitrarily" as long as it allows the previous program to have enough memory.

Line 56:

  msr cpsr_c, #0x53: This is to enable the total interrupt in management mode 

Line 64:

 sub lr, lr, #4 @ Calculate the return address. Here is ARM’s own specific value. Just remember it.

Line 65:

stmdb sp!, { r0-r12,lr } @ Save the used registers here stmdb (stm is equivalent to Push and DB (Decrement Before)) Ex: STMFD sp!, {r0-r5}; Push onto a Full Descending Stack

What this means is to push R0~R12 and lr (the content of the return value) onto the stack.

 ldmia sp!, { r0-r12,pc }^ @ Interrupt return, ^ means copy the value of spsr to cpsr Line 72: LDM (equivalent to POP and ia Increment After) This sentence means to restore the register

Saved Process Status Registers (SPSRs)

Current Program Register Status (CPSR)