Design of earthquake acceleration signal processing system using light sensing and DSP embedded technology

introduction

ARM and DSP are used as embedded technologies in seismic signal processing systems, which can well meet the requirements of seismic accelerometers for real-time, high precision and networking. Therefore, the embedded system design scheme based on ARM and DSP dual-core microprocessors using light sensors can, on the one hand, give full play to the fast signal processing capability of DSP, perform decimal operations, improve calculation accuracy, and complete the demodulation and spectrum analysis of the modulated signal of seismic acceleration; on the other hand, it can make full use of the rich on-chip system resources of ARM to realize the network transmission and display of the demodulated signal and its spectrum information. This scheme can easily and quickly realize system upgrades by only changing the software without reconstructing the circuit.

1 System composition and working principle

The seismic accelerometer consists of a sensor probe, photoelectric conversion and signal processing system. The sensor probe is composed of a fiber M-z interferometer based on 3x3 coupling and related mechanical parts. As shown in Figure 1, the input end of the interferometer is a 2x2 coupler, the output end is a 3x3 coupler, and the measured signal is added to the sensor arm of the interferometer.

The two arms of the interferometer are respectively wound on the upper and lower force arm cylinders in the sensor head. When external vibration is applied, the simple harmonic oscillator applies a longitudinal stress to the signal arm fiber, and the length of the fiber changes by ±△L (strain effect), the diameter d of the fiber core changes by ±△d (Poisson effect), and the refractive index n of the fiber core changes by ±△n (photoelastic effect). These changes will cause the phase of the light wave in the fiber to change. The phase change caused by the Poisson effect is very small compared to the strain effect and the photoelastic effect and can be ignored, thus completing the phase modulation of the acceleration signal on the optical signal. The reference arm and the signal arm are interfering in the 3x3 coupler, converting the phase change into a light intensity change. The output light intensity signal is converted into a current signal through PIN and output to the signal processing system, which can demodulate the seismic acceleration signal, perform spectrum analysis and display, and control network transmission.

2 Signal Demodulation Principle

By analyzing the simple harmonic oscillator in the sensing system, it can be concluded that the phase change of the light wave Φ(t) and the acceleration a(t) felt by the simple harmonic oscillator have the following relationship.

In the formula, E is the Young's modulus of the optical fiber; A is the cross-sectional area of ​​the optical fiber; is the stiffness coefficient of the spring sheet; is the effective optical fiber length; and m is the mass of the simple harmonic oscillator. From formula (1), it can be seen that the measured acceleration is linearly related to the optical phase change.

In the case of 3x3 coupling symmetry, the output of the three current signals output from the interferometer after passing through the I, V conversion circuit and the amplifier circuit is:

In the formula, C and B (i=1, 2, 3) are the DC component and AC gain of the three outputs respectively; is the optical phase difference caused by the measured signal. Solving Φ(t) from (2) and combining it with (1) can get the acceleration signal. The algorithm block diagram for solving Φ(t) is shown in Figure 2.

Demodulated output signal:

Combining equation (1) and equation (3), we can find the acceleration a(t).

3 Hardware Implementation of Signal Processing

The principle block diagram of the signal processing subsystem is shown in Figure 3.

With ARM (LPC2214 from Philips) and DSP (TMS320VC5402 from Ti) as the core, the system expands signal conditioning, A/D acquisition, network control and LCD display modules. ARM is used as the system control center to control the A/D converter to acquire the modulated signal of earthquake acceleration, and store the data in the DSP internal RAM through the HPI interface of DSP. It completes the network transmission control, real-time display and HPI boot loading of TMS320VC5402 of the demodulated signal. The DSP mainly performs signal calculations and completes demodulation and FFT spectrum analysis.

The LPC2214 controller has 16 kbits RAM and 256 kbits FLASH on chip. In order to facilitate system upgrade, 128 kbits external RAM and 2 Mbits external FLASH are expanded. Since DSP needs to calculate a large amount of data, the internal RAM space is limited and it is also used to store the boot loader program after power-on reset, so 128 kbits external RAM is expanded.

LPC2214 has 4 external memory groups, and for the system design in Figure 3, there are 6 ARM extended memories or external I/O devices. Therefore, the address space is subdivided using the chip select signal CS3, address lines A23, A22, A21 and a 138 decoder. This external memory or I/O device belongs to a bank, group, and the address used is 0x83000000~0x83ffffff.

3.1 Signal conditioning and A, D acquisition circuit

The main purpose of signal conditioning is to remove noise from the signal and match the measured voltage range with the AD sampling range to improve sampling accuracy. This system uses the ADA4861-3 special amplifier chip from Anolog Device. The chip integrates 3 amplifiers. It uses a single 5 V power supply. By adjusting the resistance value of the external resistor, the amplification gain of 1 to 1900 can be obtained, and the output has good linearity and temperature stability. Since the amplifier circuit is integrated in the chip, the introduction of noise is reduced.

The main performance indicators to be considered in selecting MD chips include resolution, conversion rate, number of input channels, signal-to-noise ratio, output interface and other parameters. Because the frequency of the collected acceleration signal is within 1 kHz, according to the Nyquist theorem, the sampling frequency > 2 kHz can restore the original signal without distortion. There are 3 input signals. Considering the above factors, this system uses the AD7655 chip produced by Anolog Device. The chip supports 4 inputs (INA1, INA2, INB., INB2), the conversion bit number is up to 16 bits, the conversion rate is 1MSPS, the single power supply is +5 V, the serial/parallel output mode, and the dual-channel synchronous sampling. The sampling is controlled by the A. pin level, A0=0, INA1/INB1 sampling synchronization; Ao=1, INA~NB2 sampling synchronization. The reference voltage surface is connected to 2.5 V, and the resolution is 2×VREF/655 36, which is about 76-3 V.

3.2 Interface circuit between ARM and DSP

ARM and DSP are connected through the HPI interface. ARM first writes the control word to DSP to set the working mode, then writes the access address to the address register (HPIA), and then reads and writes the data latch (HPID) to read and write the specified storage unit. The host can address the control register, address register and data register of the HPI interface through two address lines A and A[51; HBIL, HCNTL1 and HCNTL0 distinguish the high and low bytes of 16-bit data. When writing data to the address of HBIL=0, it means it is the first byte, and writing data to the address of HBIL=I means the second byte. And before data interaction, the BOB bit in the control register must be set to indicate whether the high address is in front or the low address is in front. This step is completed by ARM when the program is initialized. The chip select signal of DSP is connected to the nCS2 of the host, and the address space belongs to the bankz group, that is, 0) [82000000~0x82. The DSP can send an interrupt signal to the host through HINT to notify the host that a frame of data has been processed. After receiving the interrupt signal, the host reads the data in the agreed DSP internal data space for display or network transmission and other processing operations.

The DSP bootloader uses the HPI method, and the interrupt 2 signal is used to activate the HPI bootloader mode. There are two ways to obtain the input signal on the interrupt 2 pin: ① Directly connect the host interrupt HINT to INT2; ② Trigger a valid external interrupt INT2 within 30 clock cycles after capturing the DSP reset vector. Since the HINT signal in this design is used to generate an interrupt signal to the host, the HPI bootloader adopts method ②. Note that at the beginning of the bootloader, the HINT pin will generate a valid interrupt signal, so the ARM must clear this interrupt during initialization.

3.3 ARM and DM9Ooo network control interface

DM90OOE is an Ethernet MAC controller produced by Davicom. It supports 10/100 Mbps transmission rate. The circuit uses 16-bit bus mode for control. That is, the data bus D1~D1 is connected to the chip's SD1~SD1, the address line is also connected accordingly, and the chip select line is connected to the chip's AEN. The base address of the DM9000E Ethernet controller is Ox300. The address line A of the bus is connected to the chip's command/data enable terminal CMD, so the address to operate it is 0x300 (address port) and 0x304 (data port), and the 32-bit address obtained by combining the ARM chip select line is 0x83000300 (address port) and 0x83000304 (data port).

4 System Software Design

In traditional embedded system software design, programming is complicated due to the widespread use of single-task sequential mechanisms. At the same time, poor system security leads to frequent system resets and failure to achieve design goals. This design introduces the tzCOS-II real-time operating system in software design, making program design very simple, and transplanting the operating system to LPC2214 to improve the real-time performance of the system.

First, write the driver program that interfaces with the hardware. The application layer program uses tasks as programming objects. Tasks have parameters such as task stacks and priorities. Different priorities can be assigned according to the execution order and importance of tasks. During the task scheduling process, the OSTaskSuspend (os PRIO—SELF) and OSTaskResume (task_prio) functions can be used to switch between tasks. This system can be divided into 6 major tasks: DSP boot loader, D acquisition, reading HPI, writing HPI, network transmission, and LCD display. Create tasks in the main function and set various task parameters. The main program flow chart is shown in Figure 4.