Design of Profibus-DP master communication platform

introduction

Profibus-DP is an open fieldbus standard launched by Siemens for high-speed data transmission between field-level distributed automation peripherals. Profibus broke through the 20 million node mark in April 2007. According to PI (the world's fieldbus Profibus user organization), there are now more than 25 million nodes, and it is expected to break through 50 million nodes in 2012, with annual chip sales of 4.5 million.

At present, the research and development of related products of Profibus-DP in the domestic industry are based on the dedicated protocol chips provided by foreign countries (most of the master stations use ASPC2 launched by Siemens, and the slave stations mostly use intelligent communication chips such as SPC3), and there are no reports on the development of protocol chip prototypes. For the development of master stations, some domestic research institutes (706 Teaching and Research Office of Beihang University, Chinese Academy of Sciences, Zhejiang University, etc.) have also used programmable logic devices with MCU to design simple master station test products, but these products can only realize the functions of a single master station, which is far from the formation of a powerful Profibu-DP network. In order to break the monopoly of foreign chips and promote the development of related chips and products in China, this paper proposes a method of combining FPGA and ARM to solve the master-master communication and master-slave communication problems of Profibu-DP Class 1 master stations, and realizes a relatively complete master station development plan.

1 Profibus-DP master station communication mechanism and technical characteristics

1.1 Profibus-DP master station communication protocol

The structure of the Profibus protocol uses the OSI reference model. DP uses layer 1, layer 2 and the user interface, and layers 3 to 7 are not described. A DP system can be either a single-master structure or a multi-master structure. This article deals with a multi-master structure. The multi-master structure uses a mixed bus access control mechanism, with token control between master stations; tokens are passed between master stations, and the master station with the token has bus access control rights; the master station and the slave station adopt a master-slave control method.

A token is a special message, as shown below:

SD is the start delimiter, DA is the destination address, and SA is the source address. The token ring is an organizational chain of all master stations, and a logical ring is formed according to the address of the master station. In this ring, the token is passed between the master stations in ascending order of address within a specified time. The user writes a token passing program to ensure that each master station obtains the token within a specified time. After that, the master station can communicate with its slave stations within the specified time, and can also communicate with all master stations. The data communication between the master station and its slave stations is automatically processed by the master station according to the determined cycle order.

1.2 Token cycle time analysis

The worst case token cycle time is:

Among them, TTH is the station token holding time, TTS is the overall transmission delay of the token, and TMA is the token maintenance time. Without considering error retransmission, the overall transmission delay of N master station tokens is TTS=N·TTK, and TTk is the time required to send the token PDU (protocol data unit). The transmission time of high-priority messages is THMS, and the number of messages is M; the transmission time of low-priority messages is TLMS, and the number of messages is L.

2.2 ARM controller part program design

The ARM controller program corresponds to the DDLM direct data link mapping program, the master station communication state machine, the application layer data interface and the application layer above the Profibus communication protocol data link layer.

This design encapsulates the Profibus-DP protocol into functions in layers and calls them layer by layer.

2.2.1 Slave_Handler State Machine

The Slave_Handler state machine function block is responsible for implementing the master-slave communication function and making corresponding processing according to the slave station status. There is a fixed processing order. Each call to the Slave_Handler state machine generates a DDLM request, thereby controlling the slave station to enter the corresponding communication state. The Slave_Handler state transition diagram is shown in Figure 2.

2.2.2 Scheduler and FDL_Controller State Machine

The Scheduler state machine function block is responsible for controlling the Slave_Handler state machine. It sends a slave polling control signal to the Slave_Handler state machine to control it to gradually establish a data exchange relationship with the slave.

The FDL_Controller state machine consists of 10 FDL states and transitions between these states, as shown in Figure 3.

The main work of establishing a logical token ring is to initialize LAS and GAPL. The specific initialization process of LAS and GAPL is shown in Figure 4.

The formation of LAS marks the completion of the initialization of the logical token ring. The next step is the maintenance phase of the operation of the logical token ring. The token will be passed cyclically according to the LAS. The master station that obtains the token has the right to poll its slave stations. During the transmission process, the master station will query all addresses within its GAP range through the Request FDLStatus active frame at fixed time intervals, and modify the LAS and GAPL according to the query results. After the master station activity table is generated, the predecessor station asks for the RequestFDLStatus, and the master station replies that it is ready to enter the logical token ring and enter the Active_Idle state from the Listen_Token state (the predecessor station of the master station will modify its own GAP and LAS, and regard the master station as its successor station). The master station is in the Active_Idle state * bus, and can respond to the active frame addressed to itself, but has no right to initiate bus activities until the predecessor station transmits the token to it. It retains the token and enters the Use_Token state, in which it drives the Scheduler state machine to work. After the master station holds the token, it first calculates the time from the last time the token was obtained to the current time the token is obtained (i.e., the actual rotation time tRR), and compares it with the target rotation time tTR set by the user. If tRR is less than tTR, the master station starts to process the transmission task. High-priority transmission services are processed first, and low-priority services are processed after all high-priority services are processed. In this process, after each complete message cycle, the master station recalculates tTR-tTH. If the result is less than 0, the master station enters the PassToken state and passes the token to the successor station. The unfinished tasks will be executed when the token is held next time. After all transmission services are completed, the master station hands over the token regardless of whether there is time remaining. If the master station finds that tTR-tTH is less than 0 when it receives the token.

3 System working process

The system working process is mainly the communication interaction process between the ARM controller and the FPGA, as shown in Figure 5. Considering the system security, the FPGA and ARM must have a confirmation signal from both sides to establish communication. Although the Altera Cyclone series FP-GA has no pin output before power-on and stability, it is still not enough from the perspective of system security.

The design of the FPGA_READY signal here takes into account that the internal phase-locked loop module PLL of the FPGA needs time to establish before it can work stably, and it cannot be operated when it is not stable. The communication status is converted through the state machine on the ARM controller (FDL control state machine, scheduling state machine and master-slave communication state machine). According to the timing requirements, the information given by the slave station response frame, and error checking information, the state machine can handle general abnormalities and automatically recover to normal communication.

4 Conclusion

The Profibus-DP protocol can be implemented with any microprocessor as long as it is equipped with an internal or external asynchronous serial interface (UART), but when the data transmission rate is fast (over 500 kb/s), it is safer and more reliable to use an ASIC chip. This paper makes full use of the advantages of FPGA's good real-time performance and ARM core microcontroller's ease of development to implement the Profibus-DP Class 1 master station. After building a simple test environment for testing, it can establish communication connections with finished master-slave stations on the market and perform basic master-master and master-slave communications.