CPLD/FPGA high-speed data processing system using ARM and single-chip microcomputer

1 Introduction

Traditional data acquisition systems generally use single-chip microcomputers, and most systems complete data transmission through the PCI bus. Its disadvantages are poor mathematical computing capabilities; limited by the number of computer slots and interrupt resources; inconvenient to connect and install; and susceptible to the electromagnetic environment in the chassis. These problems have curbed the further development and application of data acquisition systems based on the PCI bus. Therefore, a simpler and more universal way is needed to complete the interaction between the acquisition system and computer data.

The performance of the data acquisition system mainly depends on its accuracy and speed. The sampling speed should be increased as much as possible under the condition of ensuring accuracy to meet the requirements of real-time acquisition, real-time processing and real-time control. Practice shows that the data acquisition system composed of ARM 32-bit embedded microprocessor as controller and USB (Universal Serial Bus) and host computer connection can greatly improve the system data processing capability and reduce the dependence on PC and interface speed.

2 System Hardware Design

The basic idea of ​​realizing the system function is to use CPLD/FPGA to realize the digital platform of the instrument, and to realize the intelligent control and high-speed data processing of the whole machine together with the ARM embedded processor and single-chip microcomputer.

2.1 System Block Diagram

The system principle block diagram is shown in Figure 1. The system is mainly composed of modules such as microprocessor, digital logic platform, input control, A, B channel input processing, C channel input processing, shaping, A/D conversion, sampling timing control, keyboard LCD display , and memory expansion.

2.2 System Structure Diagram

The system hardware is shown in Figure 2. A small-scale CPLD and a large-scale FPGA are combined to form the digital logic platform of the system. The CPLD is mainly used for input control, and the FPGA connects other parts of the system. CPLD/FPGA can realize on-site programming. Using CPLD/FPGA can make the design convenient. Its flexibility, fast verification and design can be changed at will can greatly shorten the development time.

2.3 Main functions

2.3.1 Microprocessor

The system uses the ARM 32-bit microprocessor LPC2105 produced by Philips as the main CPU for high-speed data processing, and uses the 8-bit microcontroller P89C51RD2 as the auxiliary CPU for slower data processing, controlling other peripheral chips and modules to realize the data acquisition functions of A and B channel analog bandwidth 100 MHz, peak voltage ±100 V and C channel diode on/off, voltage, current, and resistance value.

2.3.2 A, B channel part

The measured analog signal is conditioned to a range suitable for sampling by the ADC chip (AD9288) through an automatic gain circuit (AGC), i.e., a program-controlled amplifier. According to the frequency and triggering mode, the conditioned analog signal is sampled (A/D conversion) using real-time sampling or equivalent sampling. The sampled data is stored in a high-speed FIFO memory (IDT72V261LA10A).

Combined with keyboard operation and system settings, mathematical operations are performed on the sampled data, and the restored waveform data and parameters are sent to the LCD display for display or stored in the flash memory or transmitted to the PC through the USB interface, thereby realizing the function of high-speed data acquisition of A and B channels.

2.3.3 C channel part

The C input channel is a multifunctional input channel. The system selects different modules to measure voltage, current or the on/off and resistance of diodes by controlling the relay matrix. After the measured component parameters or voltage and current are processed by the multifunctional conversion circuit, the signals are sent to the 24b A/D converter ADS1211 for sampling and then sent to the single-chip microcomputer P89C51RD2 to analyze the parameter values ​​of the measured component or voltage and current, thus realizing the function of high-precision data acquisition of the C channel.

2.3.4 Keyboard and LCD display interface circuit

This system uses a 4×8 keyboard and a 320×240 LCD display module without a driver. The driver and video memory are designed in the FPGA. The above system communicates with the PC through the USB interface and realizes a visual human-computer interaction interface under the control of the host computer. At the same time, the system also retains the traditional RS 232 interface, but it is only used for programming and downloading of ARM and single-chip microcomputers.

3 Software Design Process

The LPC2105 chip serves as the main control center and data processing center of the system. The operation of the entire system is controlled by it, such as responding to user key operations, issuing channel control, A/D sampling clock control, FIFO write clock selection, menu and system status display, FIFO data processing, automatic testing of signals or parameters, etc.

The software program structure of the data acquisition card is shown in Figure 3, which can be divided into system initialization module, key analysis module, system core control module, channel control module, trigger control module, A/D sampling control module, FIFO read and write control module, frequency word reading module, parameter test module, status display module, waveform display module, storage control module, and other functional modules.

The system initialization module includes power-on self-test, hardware parameter initialization, system status initialization (such as channel waveform display status initialization), etc. The key analysis module analyzes and processes the user input on the panel, calls the corresponding function processing module through the core control module, and realizes the processing function from the key analysis by calling the channel control module, trigger control module, A/D sampling control module, FIFO read and write control module, frequency word reading module, parameter test module, status display module, waveform display module, storage control module, and other function modules. The status display module displays various states of the program when it is running, such as the current data acquisition scanning rate, the vertical sensitivity of the channel, etc. The waveform display module displays the acquired waveform.

The program of the whole system can be divided into the bottom layer driver and the upper layer software. The bottom layer driver refers to the program part that directly controls or accesses other peripherals or devices of the system, including the initialization of LPC2105 and the microcontroller (i.e., the operation assignment of each core register in the chip, the initialization assignment of the on-chip peripherals, and the control operation of each peripheral interrupt in the chip and the external interrupt). The upper layer software mainly refers to: menu design and display, data processing, waveform recovery and smoothing, etc.

4 System Performance Indicators

4.1 Performance indicators of A and B channels

(1) Analog signal bandwidth: 100 MHz (40 dB);

(2) Maximum real-time sampling rate: 100.MS/s;

(3) Maximum equivalent sampling rate: 5 GS/s;

(4) Vertical resolution: 8 b;

(5) Vertical sensitivity: 5 mV/div～25 V/diV;

(6) Horizontal scan: 5 ns/div～10 s/div;

(7) Maximum input voltage: (AC+DC) ±100 Vpp;

(8) Input RC: 1 MΩ ± 1.5% / 20 pF ± 3 pF;

(9) Coupling mode: DC, AC, grounding;

(10) Trigger mode: AC, DC, high frequency suppression, low frequency suppression;

(11) Trigger source: A, B;

(12) Storage depth: 16K/channel;

(13) Display mode: A, -A, B, -B, AB, A+B;

(14) Measurement signal parameters: period, frequency, average value, effective value, peak value, root mean square value, minimum value, maximum value, rise time, fall time, positive bandwidth, negative bandwidth, duty cycle;

(15) Measurement accuracy: ±5%;

(16) Calibration signal: 1 kHz/3.3 V.

2 C channel performance indicators

(1) Measuring resistance: 100 Ω, 1 kΩ, 10 kΩ, 100 kΩ, 1 MΩ;

(2) Measurement voltage: 10 mV, 30 mV, 1 V, 3 V, 10 V, V:

(3) Measurement current: 200 mA, 1 A;

(4) Diode: on-off measurement;

(5) Measurement accuracy: ±3%.

5 Conclusion

This system adopts the design of ARM+single-chip microcomputer+CPLD/FPGA. Its high-speed data processing task can be completed independently by the lower computer, and the system has a large-screen LCD display, so it can be used normally without the PC in the case of power failure. The acquisition card has the functions of real-time acquisition, automatic storage, instant display, instant feedback, automatic processing, automatic transmission, etc. It provides a guarantee for the authenticity, validity, immediacy and availability of field data, and can be easily input into the computer. It can be applied to intelligent instrumentation, industry, agriculture, commerce, transportation, logistics, warehousing and other industries.