SPI communication between FPGA and STM32[Copy link]
This post was last edited by From Getting Started to Giving Up on 2018-8-31 19:15 From the perspective of resource configuration, processors such as ARM and DSP integrate computing units, storage units and a large number of bus interfaces. Engineers can make the bus interface work in the corresponding mode by correctly configuring the parameters of each register. However, there are a large number of logic resources inside the FPGA, and the bus interface needs to be designed according to the needs. There are only some special modules inside it, such as PLL, DSP unit, etc. Since many interfaces need to be designed by themselves in a system built by FPGA, it will take up a lot of time for developers. Therefore, when we do projects, we often use FPGA with ARM and DSP, and FPGA often plays the role of slave, while ARM and DSP are used as master controllers. SPI acts as a bridge between the two to carry out a data exchange process. SPI is the abbreviation of Serial Peripheral Interface. It is a synchronous serial data transmission between CPU and peripheral low-speed devices. Under the shift pulse of the master device, data is transmitted bit by bit. It is full-duplex communication. Most devices transmit data in the order of high bit first and low bit last. The data transmission speed is generally faster than I2C bus, and the speed can reach several Mbps. SPI interface works in master-slave mode. This mode usually has one master device and one or more slave devices. Its interface includes the following four signals: (1) MOSI master device data output, slave device data input (2) MISO master device data input, slave device data output (3) SCLK clock signal, generated by the master device (4) CS - slave device enable signal, controlled by the master device In actual applications, the master device may need to transmit data with multiple slave devices. In theory, multiple chip select enable signals can be added, but it is relatively wasteful of I/O resources. The SPI communication module in this experiment has been improved to solve the problem that multiple slave devices need multiple chip select lines. The main device of this SPI communication module is the STM32 microcontroller, and the slave devices are the various functional modules built by FPGA. The pins of the SPI communication module are defined as follows: communication clock spi_scl, master device data output line spisdi, master device data input line spisdo, module, select chip select line spi_cs_cmd and data transmission chip select line spi_cs_data. Its working principle is: after the module selects the chip select signal spi_cs_cmd at a low level, the master device data output line spi_sdi is used to send an 8-bit module selection signal (256 modules can be selected for communication). After the module selection signal is sent, the data transmission chip select line spi_cs_data is at a low level, and the master device data output line spi_sdi is used to send 32-bit data to the selected module. When FPGA receives data, first the module selection chip select signal spi.cs__cmd becomes low level, and when the communication clock spi_scl. rises, FPGA reads the module selection signal through the master device data output line spi_sdi, using the left shift register. After 8 communication clocks, the module selection signal can be read and stored in the 8-bit module selection register dcnd; at the same time, the module selection signal reception end flag cmd done generates a high level. Similarly, when the data transmission chip select line spi_cs_data is low level, when the communication clock spi_scl. rises, FPGA reads the data signal through the master device data output line spi_sdi, using the left shift register. After 32 communication clocks, the data signal can be read and stored in the 32-bit data receiving register dout; at the same time, the data reception end flag data done generates a high level. When cmddone and datadone are high, the data output by dout and demd is valid. When FPGA sends data, first, when the data transmission chip select spi_cs_data is high, wait until the falling edge of the communication clock spi_scl arrives, and store the data to be sent by FPGA in the data transmission register din reg; when spi cs data is low, wait until the falling edge of the spi_scl clock arrives, the register din_reg data is sent to the microcontroller from the master device data input line spi_sdo through the left shift register. After 32 communication clocks, the data is sent. Verilog writing of spi.v file
spi.v(5.49 KB, downloads: 70)
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