LPC1788 startup code analysis-EEWORLD

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After creating a new project based on NXP1788 in Keil uVision4, you will be prompted to add the startup assembly code startup_LPC177x_8x.S. This file performs the initialization work from assembly to C language operating environment.

;/*****************************************************************************

; * @file: startup_LPC177x_8x.s

; * @purpose: CMSIS Cortex-M3 Core Device Startup File

; * for the NXP LPC177x_8x Device Series

; * @version: V1.20

; * @date: 07. October 2010

; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------

; *

; * ARM Limited (ARM) is supplying this software for use with Cortex-M3

; * processor based microcontrollers. This file can be freely distributed

; * within development tools that are supporting such ARM based processors.

; *

; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED

; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

; *

; *****************************************************************************/

;

Stack_Size EQU 0x00000200 ; Open up a stack space of size Stack_Size

AREA STACK, NOINIT, READWRITE, ALIGN=3

;The AREA directive is used to define the code segment and data segment, followed by the attribute label. "READWRITE" means readable and writable, "READONLY" means read-only.

;According to the data sheet, the readable and writable segment is kept in the SRAM area, the starting address is 0x1000 0000, and the stack is stored in the SRAM space.

;The read-only segment is stored in the Flash area, the starting address is 0x0000 0000, and the interrupt vector table in the code is stored in the Flash space

; The address of the top of the stack, __initial_sp (i.e. 0x1000 0200), is stored at 0x0000 0004, and the address of Reset_Handler is stored at 0x0000 0004

Stack_Mem SPACE Stack_Size

__initial_sp; label __initial_sp points to the top of the stack

;

Heap_Size EQU 0x00000400 ; Define the heap space size as Heap_Size?

AREA HEAP, NOINIT, READWRITE, ALIGN=3

__heap_base

Heap_Mem SPACE Heap_Size

__heap_limit

PRESERVE8

THUMB

;Cortex-M3 stipulates that the starting address must store the top address of the stack, that is, __initial_sp, followed by the reset entry address,

;After the kernel is reset, it will automatically take out the reset address from the lower 32 bits of the starting address to execute the reset interrupt service function.

; Vector Table Mapped to Address 0 at Reset

AREA RESET, DATA, READONLY

EXPORT __Vectors

__Vectors DCD __initial_sp ; Top of Stack ; Create interrupt vector table Vectors

DCD Reset_Handler ; Reset Handler

DCD NMI_Handler ; NMI Handler

DCD HardFault_Handler ; Hard Fault Handler

DCD MemManage_Handler ; MPU Fault Handler

DCD BusFault_Handler ; Bus Fault Handler

DCD UsageFault_Handler ; Usage Fault Handler

DCD 0 ; Reserved

DCD SVC_Handler ; SVCall Handler

DCD DebugMon_Handler ; Debug Monitor Handler

DCD 0 ; Reserved

DCD PendSV_Handler ; PendSV Handler

DCD SysTick_Handler ; SysTick Handler

; External Interrupts

DCD WDT_IRQHandler ; 16: Watchdog Timer

DCD TIMER0_IRQHandler ; 17: Timer0

DCD TIMER1_IRQHandler ; 18: Timer1

DCD TIMER2_IRQHandler ; 19: Timer2

DCD TIMER3_IRQHandler ; 20: Timer3

DCD UART0_IRQHandler ; 21: UART0

DCD UART1_IRQHandler ; 22: UART1

DCD UART2_IRQHandler ; 23: UART2

DCD UART3_IRQHandler ; 24: UART3

DCD PWM1_IRQHandler ; 25: PWM1

DCD I2C0_IRQHandler ; 26: I2C0

DCD I2C1_IRQHandler ; 27: I2C1

DCD I2C2_IRQHandler ; 28: I2C2

DCD SPIFI_IRQHandler ; 29: SPIFI

DCD SSP0_IRQHandler ; 30: SSP0

DCD SSP1_IRQHandler ; 31: SSP1

DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)

DCD RTC_IRQHandler ; 33: Real Time Clock

DCD EINT0_IRQHandler ; 34: External Interrupt 0

DCD EINT1_IRQHandler ; 35: External Interrupt 1

DCD EINT2_IRQHandler ; 36: External Interrupt 2

DCD EINT3_IRQHandler ; 37: External Interrupt 3

DCD ADC_IRQHandler ; 38: A/D Converter

DCD BOD_IRQHandler ; 39: Brown-Out Detect

DCD USB_IRQHandler ; 40: USB

DCD CAN_IRQHandler ; 41: CAN

DCD DMA_IRQHandler ; 42: General Purpose DMA

DCD I2S_IRQHandler ; 43: I2S

DCD ENET_IRQHandler ; 44: Ethernet

DCD MCI_IRQHandler ; 45: SD/MMC card I/F

DCD MCPWM_IRQHandler ; 46: Motor Control PWM

DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface

DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)

DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup

DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup

DCD UART4_IRQHandler ; 51: UART4

DCD SSP2_IRQHandler ; 52: SSP2

DCD LCD_IRQHandler ; 53: LCD

DCD GPIO_IRQHandler ; 54: GPIO

DCD PWM0_IRQHandler ; 55: PWM0

DCD EEPROM_IRQHandler ; 56: EEPROM

IF :LNOT::DEF:NO_CRP

AREA |.ARM.__at_0x02FC|, CODE, READONLY

CRP_Key DCD 0xFFFFFFFF

ENDIF

AREA |.text|, CODE, READONLY

; Reset Handler

Reset_Handler PROC

EXPORT Reset_Handler [WEAK] ;EXPORT is used to declare global

IMPORT SystemInit ; After reset, call SystemInit() main()

IMPORT __main

LDR R0, =SystemInit

BLX R0

LDR R0, =__main

BX R0

ENDP

; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler PROC

EXPORT NMI_Handler [WEAK]

B .

ENDP

HardFault_Handler\

PROC

EXPORT HardFault_Handler [WEAK]

B .

ENDP

MemManage_Handler\

PROC

EXPORT MemManage_Handler [WEAK]

B .

ENDP

BusFault_Handler\

PROC

EXPORT BusFault_Handler [WEAK]

B .

ENDP

UsageFault_Handler\

PROC

EXPORT UsageFault_Handler [WEAK]

B .

ENDP

SVC_Handler PROC

EXPORT SVC_Handler [WEAK]

B .

ENDP

DebugMon_Handler\

PROC

EXPORT DebugMon_Handler [WEAK]

B .

ENDP

PendSV_Handler PROC

EXPORT PendSV_Handler [WEAK]

B .

ENDP

SysTick_Handler PROC

EXPORT SysTick_Handler [WEAK]

B .

ENDP

Default_Handler PROC

EXPORT WDT_IRQHandler [WEAK]

EXPORT TIMER0_IRQHandler [WEAK]

EXPORT TIMER1_IRQHandler [WEAK]

EXPORT TIMER2_IRQHandler [WEAK]

EXPORT TIMER3_IRQHandler [WEAK]

EXPORT UART0_IRQHandler [WEAK]

EXPORT UART1_IRQHandler [WEAK]

EXPORT UART2_IRQHandler [WEAK]

EXPORT UART3_IRQHandler [WEAK]

EXPORT PWM1_IRQHandler [WEAK]

EXPORT I2C0_IRQHandler [WEAK]

EXPORT I2C1_IRQHandler [WEAK]

EXPORT I2C2_IRQHandler [WEAK]

EXPORT SPIFI_IRQHandler [WEAK]

EXPORT SSP0_IRQHandler [WEAK]

EXPORT SSP1_IRQHandler [WEAK]

EXPORT PLL0_IRQHandler [WEAK]

EXPORT RTC_IRQHandler [WEAK]

EXPORT EINT0_IRQHandler [WEAK]

EXPORT EINT1_IRQHandler [WEAK]

EXPORT EINT2_IRQHandler [WEAK]

EXPORT EINT3_IRQHandler [WEAK]

EXPORT ADC_IRQHandler [WEAK]

EXPORT BOD_IRQHandler [WEAK]

EXPORT USB_IRQHandler [WEAK]

EXPORT CAN_IRQHandler [WEAK]

EXPORT DMA_IRQHandler [WEAK]

EXPORT I2S_IRQHandler [WEAK]

EXPORT ENET_IRQHandler [WEAK]

EXPORT MCI_IRQHandler [WEAK]

EXPORT MCPWM_IRQHandler [WEAK]

EXPORT QEI_IRQHandler [WEAK]

EXPORT PLL1_IRQHandler [WEAK]

EXPORT USBActivity_IRQHandler [WEAK]

EXPORT CANActivity_IRQHandler [WEAK]

EXPORT UART4_IRQHandler [WEAK]

EXPORT SSP2_IRQHandler [WEAK]

EXPORT LCD_IRQHandler [WEAK]

EXPORT GPIO_IRQHandler [WEAK]

EXPORT PWM0_IRQHandler [WEAK]

EXPORT EEPROM_IRQHandler [WEAK]

WDT_IRQHandler

TIMER0_IRQHandler

TIMER1_IRQHandler

TIMER2_IRQHandler

TIMER3_IRQHandler

UART0_IRQHandler

UART1_IRQHandler

UART2_IRQHandler

UART3_IRQHandler

PWM1_IRQHandler

I2C0_IRQHandler

I2C1_IRQHandler

I2C2_IRQHandler

SPIFI_IRQHandler

SSP0_IRQHandler

SSP1_IRQHandler

PLL0_IRQHandler

RTC_IRQHandler

EINT0_IRQHandler

EINT1_IRQHandler

EINT2_IRQHandler

EINT3_IRQHandler

ADC_IRQHandler

BOD_IRQHandler

USB_IRQHandler

CAN_IRQHandler

DMA_IRQHandler

I2S_IRQHandler

ENET_IRQHandler

MCI_IRQHandler

MCPWM_IRQHandler

QEI_IRQHandler

PLL1_IRQHandler

USBActivity_IRQHandler

CANActivity_IRQHandler

UART4_IRQHandler

SSP2_IRQHandler

LCD_IRQHandler

GPIO_IRQHandler

PWM0_IRQHandler

EEPROM_IRQHandler

B .

ENDP

ALIGN

; User Initial Stack & Heap

IF :DEF:__MICROLIB

EXPORT __initial_sp

EXPORT __heap_base

EXPORT __heap_limit

ELSE

IMPORT __use_two_region_memory

EXPORT __user_initial_stackheap

__user_initial_stackheap

LDR R0, = Heap_Mem

LDR R1, =(Stack_Mem + Stack_Size)

LDR R2, = (Heap_Mem + Heap_Size)

LDR R3, = Stack_Mem

BX LR

ALIGN

ENDIF

END

The program completes the following tasks:

Open up a stack space of size Stack_Size;

The label __initial_sp points to the top of the stack;

Define the heap space size as Heap_Size;

To create the interrupt vector table Vectors, the cortex-M3 stipulates that the starting address must store the top address of the stack, namely __initial_sp, followed by the reset entry address. In this way, after the core is reset, it will automatically take out the reset address from the lower 32 bits of the starting address to execute the reset interrupt service function.

In the Reset_Handler reset interrupt function, first EXPORT declares the global nature of Reset_Handler, and then executes the external functions SystemInit and __main respectively.

The following are some explanations of the keywords in the assembler:

AREA pseudo-instruction: used to define the code segment and data segment, followed by the attribute label. "READWRITE" means readable and writable, and "READONLY" means read-only attribute. According to the storage medium described in the data sheet of LPC1788, it can be seen that the readable and writable segment is kept in the SRAM area, with a starting address of 0x1000 0000, and the stack in the code is saved in the SRAM space. The read-only segment is saved in the Flash area, with a starting address of 0x0000 0000, and the interrupt vector table in the code is saved in the Flash space. Therefore, it can be concluded that the address of the top of the stack __initial_sp (that is, 0x1000 0200) is stored at 0x0000 0004, and the address of Reset_Handler is stored at 0x0000 0004.

Figure 1: LPC1788 address map

Figure 2: The value of address 0 in debug is 0x1000 0200, which is the top address of the stack. The value of address 0x0000 0004 is 0x0000 00F9 (from the disassembly, we can see that this value is the entry of Reset_Handler as shown in the figure below).

DCD instruction: Open up memory space. The interrupt vector table is created using the function pointer in C language. Each member is a function pointer pointing to each interrupt service function.

Since then, the startup of LPC1788 has been analyzed, mainly including stack initialization and interrupt vector table initialization. LPC1788 has internal Flash, so the above point starts from the internal Flash. The starting address of the internal Flash is 0x0000 0000, and the address of the top of the stack 0x1000 0200 is stored. 0x0000 0004 stores the entry address of the reset interrupt. After LPC1788 is reset, the reset entry address is taken from 0x0000 0004, and the interrupt reset function is executed, thereby jumping to the SystemInit and main C language functions for execution.

Keywords：LPC1788 Reference address：LPC1788 startup code analysis

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