STM32 clock system architecture

1. STM32 has 5 clock sources: HSI, HSE, LSI, LSE, and PLL.

  　  ①HSI oscillator (RC oscillator) clock is a high-speed internal clock, which is rarely used because its accuracy is not as high as that of an external high-speed clock (crystal oscillator).

　　 ②HSE is a high-speed external clock connected to a quartz/ceramic resonator, or an external clock source, with a frequency range of 4MHz~26MHz. The M4 development board is 8M         

        ③LSI is a low-speed internal clock, RC oscillator, with a frequency of 32kHz to provide a low-power clock. Mainly used for independent watchdog and automatic wake-up unit.

　　 ④LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768kHz. It is used to drive the RTC clock (RTCCLK)

　　 ⑤PLL is the phase-locked loop frequency multiplication output (frequency multiplication clock). STM32F4 has two PLLs:

    1. The main PLL (PLL) is provided with a clock signal by the HSE or HSI and has two different output clocks.

            The first output PLLP is used to generate a high-speed system clock (up to 168MHz)

            The second output PLLQ is used to generate the USBOTG FS clock (48MHz), the random number generator clock and the SDIO clock.

    2. A dedicated PLL (PLLI2S) is used to generate an accurate clock, thereby achieving high-quality audio performance on the I2S interface.

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2. The system clock SYSCLK can come from three clock sources:

        ①, HSI oscillator clock

        ②HSE oscillator clock

        ③PLL clock

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3. Clock Tree

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4. The clock frequency of the development board does not match that of the system. How to modify it?

1. Check line 177 of the assembly file startup_stm32f40_41xxx.s

Reset_Handler PROC // Reset interrupt execution

EXPORT Reset_Handler [WEAK] // Reset interrupt execution

IMPORT SystemInit //Entry for system clock initialization

IMPORT __main

       LDR R0, =SystemInit // System clock initialization

       BLX R0

       LDR R0, =__main // Start main

       BX

       ENDP

2. Check line 252 of system_stm32f4xx.c

PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N

PLL_VCO = (8000000 / 8) * 336

Calculation formula: SYSCLK = PLL_VCO / PLL_P = 336*1000000 / 2 == 168000000 == 168000KHz == 168MHz

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Modification: system_stm32f4xx.c line 254

#define PLL_M 25

change into:

#define PLL_M 8

Modify line 127 of stm32f4xx.h

#if !defined (HSE_VALUE)

#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */

change into:

#if !defined (HSE_VALUE)

#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz *

(If you cannot modify: permission problem:) Click the name to see the path, find .h and modify the permissions

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According to the document, we can understand the bus clock frequency of our development board:

System clock frequency: Standard frequency is 168MHz

AHB clock frequency: 168MHz

APB1 clock frequency: 42MHz

APB2 clock frequency: 84MHz

Overclocking: Increase the CPU's operating clock frequency.

Adjust PLL_N to 432;

Underclocking: Lowering the CPU's operating clock frequency.

Adjust PLL_N to 168;