STM32 reset and clock

Reset

        STM32F supports three reset forms, namely system reset, power reset and backup area reset.
1.1 System reset
When one of the following events occurs, a system reset is generated:
1. Low level on the NRST pin (external reset)
2. Window watchdog count termination (WWDG reset)
3. Independent watchdog count termination (IWDG reset)
4. Software reset (SW reset) (Set the SYSRESETREQ bit in the Cortex-M3 interrupt application and reset control register to 1 to achieve software reset.)
5. Low power management reset
The source of the reset event can be confirmed by checking the reset status flag bit in the RCC_CSR control status register.
1.2 Power reset (power reset will reset all registers except the backup area, address 0x0000_0000~0x0000_0004)
1. Power on/off reset (POR/PDR reset)
2. Return from standby mode
1.3 Backup area reset
1. Software reset, backup area reset can be generated by setting the BDRST bit in the backup area control register RCC_BDCR.

2. Under the premise that both VDD and VBAT are powered off, powering on VDD or VBAT will cause the backup area to reset.

clock

        Three different clock sources can be used to drive the system clock (SYSCLK): (HSE clock, HSI clock, PLL, LSE clock, LSI clock, system clock (SYSCLK, HSI clock at the beginning of power-on, HSI is turned off when HSE clock is ready), clock security system (CSS), RTC clock, watchdog clock)

1 HSI oscillator clock
2 HSE oscillator clock
3 PLL clock
These devices have the following 2 secondary clock sources:
1 32kHz low speed internal RC, can be used to drive independent watchdog and RTC. RTC is used to automatically wake up the system from stop/standby mode.
2 32.768kHz low speed external crystal can also be used to drive RTC (RTCCLK).

Special: Clock Security System (CSS), once CSS is activated and HSE clock fails, CSS interrupt is generated and NMI is also automatically generated.