MSP430F5438 study notes timer TA1 compare match CCR0

// Clock defaults  

// FLL clock FLL select XT1  

// Auxiliary clock ACLK selects XT1 32768Hz  

// Main system clock MCLK selection DCOCLKDIV 8000000Hz  

// Subsystem clock SMCLK selection DCOCLKDIV 8000000Hz  

// TA1 selects ACLK, the maximum count value is 16384, and the interrupt frequency is 2HZ  

// Toggle P4.0 in TIMER1_A0_VECTOR  

#include   

#include   

void clock_config(void);  

void select_xt1(void);  

void dco_config(void);  

int main(void)  

{  

    clock_config(); // Initialize the clock  

    P4DIR |= BIT0; //P4.0 output  

    TA1CCTL0 = CCIE; // Enable TA1CCR0, compare match interrupt  

    TA1CCR0 = 16384; // Initialize the maximum value, the compare match interrupt frequency occurs 32768/16384 = 2Hz  

    TA1CTL = TASSEL_1 + MC_1 + TACLR; // Select ACLK, the maximum value is CCR0, clear the count value  

    _EINT(); // Initialize global interrupt  

    while(1)  

    {  

        ;  

    }  

}  

void clock_config(void)  

{  

    WDTCTL = WDTPW + WDTHOLD; // Stop watchdog  

    select_xt1(); // Select XT1  

    dco_config(); // ACLK = XT1 = 32.768K  

                                                // MCLK = SMCLK = 8000K  

}  

void select_xt1(void)  

{  

    // Start XT1  

    P7SEL |= 0x03; // P7.0 P7.1 peripheral function  

    UCSCTL6 &= ~(XT1OFF); // XT1 is turned on  

    UCSCTL6 |= XCAP_3; // Internal capacitor  

    do  

    {  

        UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 error flag  

    }while (UCSCTL7&XT1LFOFFG); // Check XT1 error flag  

}  

void dco_config(void)  

{  

    __bis_SR_register(SCG0); // Disable FLL function  

    UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx  

    UCSCTL1 = DCORSEL_5; // DCO maximum frequency is 16MHz  

    UCSCTL2 = FLLD_1 + 243; // Set DCO frequency to 8MHz  

                                                // MCLK = SMCLK= Fdcoclkdiv = (N+1)X(Ffllrefclk/n)  

                                                // N is the only value that needs to be calculated  

                                                // Ffllrefclk FLL reference clock, default is XT1  

                                                // n takes the default value, which is 1  

                                                // (243 + 1) * 32768 = 8MHz  

    __bic_SR_register(SCG0); // Enable FLL function  

    // Necessary delay  

    __delay_cycles(250000);  

    // Clear the error flag  

    do  

    {  

        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);  

                                                // Clear all oscillator error flags  

        SFRIFG1 &= ~OFIFG; // Clear oscillator error  

    }while (SFRIFG1&OFIFG); // Wait for clear completion  

}  

#pragma vector=TIMER1_A0_VECTOR  

__interrupt void TIMER1_A0_ISR(void)  

{  

    P4OUT ^= BIT0;  

}