MSP430F5438 study notes DCO frequency multiplication to 8MHZ

1. Platform Description MS430F5438

1. // Clock defaults  

2. // FLL clock FLL select XT1  

3. // Auxiliary clock ACLK selects XT1 32768Hz  

4. // Main system clock MCLK selection DCOCLKDIV 1048576Hz  

5. // Subsystem clock SMCLK selection DCOCLKDIV 1048576Hz  

6. #include   

7. void clock_config(void);  

8. void select_xt1(void);  

9. void dco_config(void);  

10.   

11. int main(void)  

12. {  

13.     clock_config(); // Initialize the clock  

14.   

15.     P4DIR |= BIT0; //P4.0 output  

16.   

17.     while(1)  

18.     {  

19.         P4OUT ^= BIT0;  

20.         __delay_cycles(1000000);  

21.     }  

22. }  

23.   

24. void clock_config(void)  

25. {  

26.     WDTCTL = WDTPW + WDTHOLD; // Stop watchdog  

27.     select_xt1(); // Select XT1  

28.     dco_config(); // ACLK = XT1 = 32.768K  

29.                                                 // MCLK = SMCLK = 8000K  

30. }  

31.   

32. void select_xt1(void)  

33. {  

34.     // Start XT1  

35.     P7SEL |= 0x03; // P7.0 P7.1 peripheral function  

36.     UCSCTL6 &= ~(XT1OFF); // XT1 is turned on  

37.     UCSCTL6 |= XCAP_3; // Internal capacitor  

38.     do  

39.     {  

40.         UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 error flag  

41.     }while (UCSCTL7&XT1LFOFFG); // Check XT1 error flag  

42. }  

43.   

44. void dco_config(void)  

45. {  

46.     __bis_SR_register(SCG0); // Disable FLL function  

47.     UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx  

48.     UCSCTL1 = DCORSEL_5; // DCO maximum frequency is 16MHz  

49.     UCSCTL2 = FLLD_1 + 243; // Set DCO frequency to 8MHz  

50.                                                 // MCLK = SMCLK= Fdcoclkdiv = (N+1)X(Ffllrefclk/n)  

51.                                                 // N is the only value that needs to be calculated  

52.                                                 // Ffllrefclk FLL reference clock, default is XT1  

53.                                                 // n takes the default value, which is 1  

54.                                                 // (243 + 1) * 32768 = 8MHz  

55.     __bic_SR_register(SCG0); // Enable FLL function  

56.   

57.     // Necessary delay  

58.     __delay_cycles(250000);  

59.   

60.     // Clear the error flag  

61.     do  

62.     {  

63.         UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);  

64.                                                 // Clear all oscillator error flags  

65.         SFRIFG1 &= ~OFIFG; // Clear oscillator error  

66.     }while (SFRIFG1&OFIFG); // Wait for clear completion  

67. }  

68.