Embedded configuration mode based on microprocessor and FPGA

   Programmable logic devices ( PLDs ) are widely used in various circuit designs. Large-scale PLD/FPGA based on lookup table technology and SRAM process has high density and many triggers, which is suitable for complex sequential logic, such as digital signal processing and various algorithm designs. Such devices use SRAM cells to store configuration data. Configuration data determines the internal interconnection and function of PLD. Changing the configuration data also changes the logical function of the device. SRAM programming time is short, which creates conditions for the system to dynamically change the logical function of PLD. However, since SRAM data is volatile, the configuration data must be stored in a non-volatile memory outside the PLD device to achieve online reconfiguration (ICR).

1 In application configuration (dynamic configuration)

    同一设备在实现不同的应用时，要求FPGA实现不同的功能。如手持多媒体设备，可拍摄分辨率较高的静止图像照，采用JPEG2000压缩，也可传送活动图像，采用H.263，H.264/AVC等。单纯使用软件实现速度慢，需要对算法进行精细的优化;而使用硬件实现则速度快，但灵活性差。为此，采用微处理器和FPGA相结合来实现手持多媒体终端，微处理器实现程序控制，FPGA实现大量的规则运算。此外，手持设备的某些应用(如静止图像和活动视频压缩)可能并不同时实现。若在一片FPGA同时实现这些功能，不仅布线复杂，功能难以实现，而且需要更大规模的FPGA。若使用不同的配置数据进行配置，使FPGA在不同时刻实现不同的功能，则FPGA的容量可以显著降低，从而降低设备的体积、功耗及成本。

Figure 1 APEX FPGA Active Serial (PS) Configuration Timing Diagram

   使用在应用配置时，首先把应用分集，可能同时运行的应用分成一组，耗时的规则运算由FPGA实现，其它由微处理器实现。把一个FPGA芯片的多个配置文件连续地存放在系统存储器中，在程序执行时，微处理器把对应特定应用的配置数据装载到FPGA中并完成初始化，在FPGA进入用户模式后就能实现特定的功能了。这种方法可以采用更小规模的FPGA，不必使用专用的昂贵配置芯片(如ALTERA的EPC1、EPC2等)来存储配置数据，因而可显著地节省系统成本。

    The configuration methods of ALTERA SRAM FPGA are mainly divided into two categories: active configuration and passive configuration. In the active configuration method, the PLD device guides the configuration operation process, which controls the external memory and initialization process; while in the passive configuration method, the configuration process is controlled by an external computer or controller. According to the number of data lines, the PLD device configuration method can be divided into two categories: parallel configuration and serial configuration. The following uses the ALTERA APEX20KC series device as an example to introduce two configuration methods that are simple to connect and easy to use in the microprocessor system: passive serial configuration and passive parallel asynchronous configuration.

2 Passive Serial Configuration (PS)

     The main configuration pins for passive serial configuration are as follows:

nSTATUS: The status output of the device in the command state. After power-on, the FPGA immediately drives this pin to a low potential and then releases it within 5μs. NSTATUS is pulled up to Vcc through a 10kΩ resistor. If an error occurs in the configuration, the FPGA pulls it low. During configuration or initialization, if the configuration circuit pulls nSTATUS low, the FPGA enters an error state.

NCONFIG: Configuration control input. A low potential resets the device, and a low-to-high potential jump starts configuration.

CONF_DONF: Bidirectional open drain; it is a status output before and during configuration, and the FPGA drives it low. After all configuration data is received without error and the initialization clock cycle begins, the FPGA sets it to tri-state, and because of the pull-up resistor, it turns it to a high level, indicating that the configuration is successful. At the end of configuration and the beginning of initialization, CONF_DONE is a status input: if the configuration circuit drives this pin to low, the initialization work is postponed; inputting a high potential guides the device to perform the initialization process and enter the user state.

DCLK: Clock input, provides clock for external data source.

nCE: FPGA device enable input. When nCE is low, it enables the configuration process. For single-chip configuration, nCE must always be low.

nCEO: Output (specially for multi-chip devices). After the FPGA configuration is completed, the output is low. When multiple chips are cascaded, it drives the nCE terminal of the next chip.

DATA0: Data input, one bit of configuration data on the DATA0 pin.

PORSEL: Dedicated input used to set the power-on reset (POR) delay time.

Figure 2 Passive serial configuration scheme using a microprocessor

   nIO_PULLUP: Input. When low, enables the internal weak pull-up resistor to pull the user pin to VCCIO before and during configuration.

     Almost all ALTERA FPGA devices support passive serial configuration. The sequence diagram of passive serial configuration is shown in Figure 1. In this configuration mode, there is no handshake signal. The operating frequency of the configuration clock must be within the range allowed by the device, and there is no limit on the minimum frequency. In order to start configuration, the VCCINT and VCCIO of the bank where the configuration pins and JTAG pins are located must be powered. After the FPGA is powered on, it enters the reset state. nCONFIG is set to a low level, which puts the FPGA into the reset state; the potential jump of nCONFIG from low to high starts the configuration process. The entire configuration includes three stages: reset, configuration, and initialization. When nSTATUS or nCONFIG is low, the device leaves the reset state and releases the open-drain nSTATUS pin. After nSTATUS is released, it is pulled high by an external resistor. At this time, nSTATUS and nCONFIG are both high, and the FPGA is ready to receive configuration data, and the configuration stage begins. During the serial configuration process, the FPGA latches the data on the DATA0 pin at the rising edge of DCLK. After all data is successfully received, the CONF_DONE pin is released and pulled high by an external resistor. The transition of CONF_DONE from low to high marks the end of configuration and the start of initialization. After that, DCLK must provide several cycles of clock (the specific cycle data is related to the frequency of DCLK) to ensure that the target chip is initialized correctly. After initialization, the FPGA enters the user working mode. If the optional INIT_DONE signal is used, after the initialization is completed, INIT_DONE is released and pulled high by an external resistor, and then enters the user mode. DCLK, DATA, and DATA0 cannot be tri-stated after configuration and can be set high or low.

     During the configuration process, if an error occurs, the FPGA will pull nSTATUS low. The system can monitor in real time and restart the configuration process when this signal is recognized. NCONFIG changes from high to low and then high again to reconfigure. Once nCONFIG is set low, nSTATUS and CONF_DONE will also be set low by the FPGA. When nSTATUS and nCONFIG are both high, configuration begins.

    Figure 2 is a simplified circuit diagram of the passive serial configuration scheme of the FPGA using a microprocessor. The configuration process is: the microprocessor sets nCONFIG low and then high to initialize the configuration; after detecting that nSTATUS becomes high, the configuration data and shift clock are sent to the DATA0 and DCLK pins respectively; after sending the configuration data, it detects whether CONF_DONE becomes high. If it does not become high, it means that the configuration has failed and the configuration process should be restarted. After detecting that CONF_DONE becomes high, a certain number of clocks are sent to the DCLK pin according to the timing number of the device; after the FPGA is initialized, it enters the user mode. If the microcontroller has a synchronous serial port, DATA0 and DCLK use the serial data output and clock output of the synchronous serial port. At this time, it is only necessary to simply latch the data byte or word into the transmit buffer. When using ordinary I/O lines to output data, DCLK must be set low and then high to generate a rising edge for each bit output. It uses the memory more efficiently than the circuit connection diagram given in the ALTERA manual.

Figure 3 Passive parallel asynchronous configuration circuit using a microprocessor

3 Passive parallel asynchronous configuration

    Like passive serial configuration, passive parallel asynchronous configuration also includes three stages: reset, configuration, and initialization. The passive parallel asynchronous configuration circuit diagram is shown in Figure 3. When nSTATUS or nCONFIG is low, the device is in reset state. The microprocessor generates a low-to-high jump at the nCONFIG pin to start the configuration of the FPGA. When nCONFIG becomes high, the device is out of reset state and releases the open-drain nSTATUS pin. The FPGA is ready to receive configuration data and the configuration stage begins. In the configuration stage, the microprocessor FPGA is used as a memory to perform write operations, that is, the microprocessor first enables the chip select, then sends 8 bits of data to the Data[0:7] pin, and configures the pin RDYnBSY to a low level, indicating that the FPGA is busy processing configuration data and the microprocessor can perform other functions. During the low level of RDYnBSY, the FPGA uses the internal oscillator clock to process the configuration data. When the FPGA is ready to receive the next byte of configuration data, it drives RDYnBSY to a high level. The microprocessor detects this high level and sends the next byte of data to the configuration pin. In order to save an I/O line for detecting RDYnBSY, the FPGA can be read by reading the memory, where nRS is the memory read signal. During the period when nRS is valid, the RDYnBSY signal is sent to the data line D7. It is also possible not to detect RDYnBSY or read the FPGA, and simply wait for the delay tBUSY(max)+tRDY2WS+tW2SB before writing down the next byte of configuration data. After processing each byte of configuration data, if an error is found, the FPGA will pull nSTATUS low, indicating that the configuration is wrong. The microprocessor can detect this error and reconfigure it. Just like the passive serial configuration, after the FPGA correctly receives all the configuration data, it will release the CONF_DONE signal, so the pin is pulled high by the external pull-up resistor, indicating that the configuration is over and the initialization begins.

4. Generation of configuration data files

    Altera's MAX+PLUS II or Quartus II development tools can generate configuration files in multiple formats for different configuration methods. The size of the configuration data varies for different target devices. The size of the configuration file is generally determined by the binary file (extension .rbf). The software tools provided by Altera do not automatically generate .rbf files. You need to follow the steps below to generate them: ① In the MAX+PLUS II compilation state, select the Convert SRAM Target File command in the File menu; ② In the Convert SRAM Target File dialog box, specify the file to be converted and select the output file format as .rbf (Sequential), then confirm.