Design and implementation of CPU master control module based on CPCI bus

　　Computers used under certain specific conditions (such as harsh environments and military application environments) generally have higher and stricter requirements than ordinary commercial computers in the following aspects: good adaptability to climate, mechanical and electromagnetic environments, good reliability, availability, maintainability, operability, human-computer interaction performance, small size, light weight, low power consumption, scalability, easy upgrade and long service life. Sometimes there are some specific requirements in some application scenarios, such as requirements on the type and number of user interfaces.

　　In the case that it is difficult to find a commercial computer that meets specific requirements, and even if a mature commercial computer is reinforced, it is difficult to meet specific requirements, it is necessary to develop a reinforced computer that meets specific requirements. Here we introduce the design of a reinforced computer based on the CPC I bus CPU main control module.

　　The Compact PCI (CPCI) bus is an industrial computer bus standard launched by the "PCI Bus Industrial Computer Manufacturers Organization". Its application has developed most rapidly in recent years. It is developed from the general bus PCI on PCs. It has many advantages of the PCI bus, such as high bandwidth, high performance, plug-and-play, and low price, and the reliability of the passive backplane bus VME bus. The main control module based on the CPCI bus mainly completes the functions of a general computer motherboard, including the main processor and related support logic, main memory, PCI bus arbitrator, system interrupt controller, PCI clock generator and general I/0 interface (IDE, USB, PS/2 keyboard and mouse, etc.) functions. It also integrates a PCI-PCI bridge PCI2050B, which provides arbitration capabilities for 7 PCI peripheral cards.

　　1 CPU main control module principle design

　　There are two main methods for designing the master control module based on CPCI bus: 1) Using device groups to design the system board. The advantage of this method is that the logic is clear, and the device can be replaced to make it work normally when the function is not normal. The designed system board has stronger vibration and mechanical shock resistance; its disadvantages are difficulty and long development cycle. With the increase of CPU speed, the design difficulty is greater, and it is difficult to buy a chipset with a wide temperature range. 2) Using embedded CPU module. This module has high integration and small size. It integrates almost all the functions of the computer. Users can complete the design by simply expanding the functions it does not have externally according to the requirements of specific tasks. The advantages of this method are short design and production cycle, convenient debugging, easy upgrade, and there are manufacturers who provide embedded CPU modules with a wide temperature range, which are also used in military fields with relatively harsh environmental requirements. In view of the short project development cycle, this design adopts the second method. Based on the CPCI bus master control module, the ETX (Embedded Technology eXtended) PM module of Kontron is used, and the PCI expansion technology is used to complete the design of the 6U CPCI bus system board. The block diagram of the CPCI master control module is shown in Figure 1.

　　1.1 ETX module

　　The ETX embedded computer module has complete PC functions and efficient CPU performance. It is a highly integrated computer system that uses an x86 CPU. The main frequency of the ETX PM is 1.0 to 1.8 GHz, and the memory can reach 1 GB. The ETX structure motherboard is mainly aimed at designers of special computer system boards. Its core concept is to "design the PC into the customer's target application system like a device." In its size of 114mm (length) x95 mm (width) × 16 mm (height), it integrates all the functions of a standard PC and provides all the standard interfaces of a standard PC architecture.

　　The ETX module contains high-performance x86 series CPU device groups, north and south bridges, display devices, network devices, audio controllers, Super I/0 controllers, etc. The back uses a high-density surface-mount connector, and the 4x100-pin bus pins define the standard interface signals of the PC as well as PCI and ISA signals. When designing the main control module, the corresponding 4x100-pin socket is designed on the main control module, and the extended I/0 function can be realized through PCI or ISA on the bus. The signals provided by each connector are as follows:

　　1) ETX connector X1: PCI bus (32-bit), USB, sound card; 2) ETX connector X2: ISA bus (16-bit); 3) ETX connector X3: VGA, LCD (LVDS), COM1, COM2, IrD-A, keyboard/mouse; 4) ETX connector X4: EIDE (×2), Ethernet, power management and other signals.

　　ETX: The PM module only provides 4 PCICLKs and 4 pairs of REQ#/GNT# signals to the outside, so it can only drive 4 PCI functional devices. To meet the requirements of the CPCI bus master module to drive 7 expansion slots, a PCI-PCI bus bridge can be added between the ETX PM module and the CPCI system bus connector to achieve bus expansion. The PCI-PCI bus bridge acts as a load on the upper bus and can drive a bus segment downward. The ETX PM module can work under the conditions of -40 to 85°C, and the ETX series products have a long life cycle and are interchangeable.

　　1.2 PCI Bridge Design

　　In the design of the master control module of this solution, the industrial-grade PCI-PCI bridge device PCI2050BI from Texas Instruments is selected. It provides a bridge connection between two 32-bit PCI buses with a maximum operating frequency of 66 MHz. The bridge supports burst mode transfers, which greatly increases the data throughput. The bus data paths of the bridge work independently. The master and slave PCI buses of the bridge can work in 3.3 V or 5 V working environments respectively, and the core logic of the bridge works at 3.3 V to reduce power consumption. PCI2050BI can carry 9 devices. In addition to providing internal arbitration for each device, the system can also provide external arbitration. PCI2050BI provides 10 device clock outputs. Using PCI2050BI to expand the PCI-PCI bus bridge, its design block diagram is shown in Figure 2. [page]

　　The system design mainly includes:

　　1) PCI2050BI has two independent clock domains. The master interface is controlled by the master input clock P_CLK, and the slave interface is controlled by the slave input clock S_CLK. These two clocks can be independent of each other, but must be synchronized. The maximum delay between P_CLK and S_CLK must not exceed 7 ns, and S_CLK cannot be ahead of P_CLK.

　　2) The slave side of PCI2050BI outputs clocks, and each clock can only drive one load;

　　3) The slave side of PCI2050BI has 10 clock outputs S_CLK[9:0], 9 of which can be supplied to the extended PCI slot, and the other S_CLK0UT9 signal must be fed back to the input clock S_CLK of the slave bus;

　　4) In order to reduce the signal reflection of the clock, the 9 CLKs output to the expansion slot must be matched with series resistors at the beginning. The resistance value of the matching resistor is related to the characteristic impedance of the circuit board. For a 65 Ω transmission line, a 50 ΩQ series matching resistor is selected;

　　5) The PCI slave bus control signals on the CPCI master module must be pulled up to ensure stability when no device is in use. These signals include: FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PERR#, SERR#, L0CK#, INTA#~INTD#. The size of the resistor depends on the load of the device. In this design, the typical value of the resistor is 8.2 kΩ;

　　6) In order to reduce the impact of the main control module on the baseboard, except for the CLK, REQ# and GNT# signals, other PCI signals must be connected in series with a 10 Ω terminal matching resistor;

　　7) Correctly set the signal environment of the bus. The PCI bus signal environment of ETX PM is 3.3 V. When designing, connect the P_VCCP of PCI2050BI to 3.3 V; S_VCCP is connected to the VIO of the backplane, which may be 3.3 V or 5 V according to the setting of the backplane VIO voltage, thus completing the setting of the signal environment.

　　1.3 IDE interface

　　On the main control module based on CPCI bus, a 32GB wide temperature electronic hard disk is expanded, and the IDE interface is used as the storage space of the operating system or application program. Integrated drive circuit (IDE) is applicable to any drive with an integrated (built-in) disk controller. IDE devices generally include hard disks, optical drives, etc. Because the CPU main control module of this design is mainly used in computers in harsh environments, the working temperature and vibration resistance of electronic disks are much better than ordinary hard disks, so when the system boots, a 32 GB wide temperature electronic hard disk is expanded on the main control module based on CPCI bus. The ETX module provides two IDE channels (PRAMARY IDE and SEC0NDARY IDE), and each channel can connect to two IDE devices. The interface of ordinary IDE devices is generally a 40-pin signal port, and the power supply of IDE devices is provided by another separate power supply interface. The IDE interface of the electronic disk is generally 44 pins, and the first 40 pins are consistent with the definition of the ordinary IDE device interface, and the last 4 pins are the power supply interface of the electronic disk, and the electronic hard disk only uses a 5 V power supply. Therefore, in this design, the PRIMARYIDE-44 pin interface is placed on the CPU main control module to connect the electronic hard disk as a system disk. The SECONDARY IDE is connected to the rear wiring board through the rear wiring board interface P2 to connect to a normal hard disk or optical drive.

　　2 PCB Layout

　　2.1 Component packaging selection

　　All electronic components in this design are surface mount components. Most resistors and capacitors are packaged in 0603, and resistor rows are used extensively. Since only surface welding is done, drilling is not required, the size is small, the power consumption is low, the printed circuit board space is saved, and the layout and routing of the entire board are simplified.

　　2.2 PCB layer selection

　　This design chooses to make an 8-layer PCB board. The standard bus connector pin spacing of CPCI board is 2.0 mm, the pad aperture is 0.6 mm, and the pad diameter is 1.1 mm, so the routing space between the two pads is only 0.9 mm, the line width is 6 mil, and only 2 lines with a line spacing of 6 mil can be routed in a single layer, while the CPCI bus connector has 5 pins in a single row, that is, 5 lines must be routed, so the signal layer cannot be less than 3 layers. For the main control module, its main power supply is 3.3 V and 5 V. In order to ensure the symmetry of the signal layer and the power layer, and considering the complexity of this board and the integrity of the signal, the signal layer is designed as 4 layers, and the ground plane and the electrical plane are designed as 2 layers respectively. The final layer distribution design of the printed circuit board is: top signal layer, ground layer 1, inner signal layer 1, 3.3 V electrical layer, ground layer 2, inner signal layer 2, 5 V electrical layer, bottom signal layer.

　　2.3 PCB layout

　　In the design and wiring process of the CPCI master control module, the PCI2.1 specification and PICMG2.0R3.0 specification are strictly followed, and high-precision, shielded, pinhole CPCI connectors that comply with the IEC-1076 international standard are used. Among the five CPCI connectors J1, J2, J3, J4, and J5 on the master control module, J1 and J2 connectors are used to connect PCI bus signals, while J3, J4, and J5 connectors are used to expand the IO signals of the system board. The designed master control module can drive seven CPCI expansion slots.

　　When designing the PCB layout and wiring of the CPCI main control module, the design points are as follows:

　　1) The length of the transmission line from the PCICLK of the ETX module to the clock P_CLK signal of the PCI2050BI main bus must be 8.7±0.1 inches;

　　2) To reduce the skew between the clocks on the CPCI backplane bus, the S_CLKOUT9 signal of the PCI2050BI slave bus must be fed back to the S_CLK of the slave bus, and the 9 clock lines (9 S_CLKOUT) supplied by the PCI2050BI to the expansion slot must be of equal length to the S_CLK.

　　3) Provide a 0.1μF high-speed decoupling capacitor for each power pin of PCI2050BI, and try to keep it close to the power pin of PCI2050BI when wiring;

　　4) When wiring the main control module, place PCI2050B as close to the J1 and J2 connectors as possible to make the distance from the PCI bus signal to the connector as short as possible;

　　5) According to CPCI specification, the 10Ω terminal matching resistor of PCI bus signal line should be set within 15.2mm of the connector pin of the signal. These bus signals include AD0~AD31, C/BE0#~C/BE3#, PAR, FRAME#, IRDY#, TRDY#, STOP#, L0CK#, IDSEL, DEVSEL#, PERR#, SERR# and RST#;

　　6) Ethernet port signals and USB signals are differential signals. Differential lines should be used when routing on the printed circuit board. For Ethernet port signals TX+ and TX-, RX+ and RX-, differential line pairs should be used. For USB signals USB+ and USB-, differential line pairs should be used.

　　7) IDE signal cables should be as long as possible to ensure transmission quality;

　　8) All PCI signal lines must be impedance controlled, with an impedance of 65Ω±10%.

　　3 Conclusion

　　The CPCI bus is a high-speed synchronous shared bus, and the ETX module has the characteristics of powerful performance, high reliability, flexible structure, excellent scalability and compact size. It provides a solution for the rapid self-development of a 6U master control module based on the CPCI bus. Through in-depth analysis of the CPCI bus characteristics and a deep understanding of the high-frequency digital circuit design method, a master control module based on the CPCI bus has been successfully developed. Comprehensive tests and actual application verification show that the module has reached the performance indicators required by the system, the system works stably, and all interfaces are applied normally.