Research and software design of simulating I2C bus multi-master communication

　　I2C bus (Inter IC BUS) is a two-way two-wire serial communication standard launched by Philips. It has been widely used due to its advantages of few interfaces and high communication efficiency [1~3]. In addition to simple single-master node communication, it can also be used in multi-master node communication systems. In a multi-master node communication system, if two or more master nodes start data transmission at the same time, the bus has conflict detection and arbitration functions to ensure normal communication and prevent data corruption. Many microcontrollers (MCUs) now have I2C bus interfaces, which can facilitate I2C bus design. For MCUs without I2C bus interfaces, two I/O interface lines can be used for simulation [2, 3]. At present, some materials introducing simulated I2C mainly talk about communication in a single-master node system, which makes the application of simulated I2C bus have certain limitations. Based on the idea of ​​bus arbitration, this paper proposes an idea and implementation process for multi-master node communication.

1 Introduction to I2C bus system [1~3]

　　The I2C bus system is composed of two buses: SCL (serial clock) and SDA (serial data). The bus has strict timing requirements. When the bus is working, the serial clock line SCL transmits clock pulses, and the serial data line SDA transmits data. The bus protocol stipulates that each master node must have start, end, data transmission and response signals when communicating. These signals are the basic units in the communication process. Each frame of data transmitted by the bus is 1 byte. Every time a byte is sent, the receiving node will give a response signal accordingly. The protocol stipulates that the high 7 bits of the first byte after starting the bus are the addressing address of the slave node, the 8th bit is the direction bit ("0" indicates the master node writes to the slave node; "1" indicates the master node reads from the slave node), and the remaining bytes are operation data. Figure 1 lists the timing of several basic signals on the I2C bus.

　　Figure 1 includes the start signal, stop signal, response signal, non-response signal, and the timing of transmitting data "0" and data "1". The start signal is when the SDA line changes from high to low when the SCL line is high; the stop signal is when the SDA line changes from low to high when the SCL line is high; the response signal is when SDA is low when SCL is high; the non-response signal is the opposite, when SDA is high when SCL is high. The timing diagrams for transmitting data "0" and data "1" are the same as those for sending response bits and non-response bits.

Figure 1 Timing of basic signals on the I2C bus

　　Figure 2 shows a complete data transmission process. After the I2C bus sends the start signal, it sends the slave's 7-bit address and 1-bit read/write bit indicating the nature of this operation. After receiving the response signal, it starts to transmit data until the stop signal is sent. The data is in bytes. Every time the sending node sends a byte, it will detect whether the SDA line has received a response signal. If it has, it will continue to send, otherwise it will stop sending data.

Figure 2 A complete data transmission process

2 Arbitration of I2C Bus

　　In a multi-master communication system. There are multiple nodes on the bus, and they all have their own addressing addresses. They can be accessed as slave nodes by other nodes. At the same time, they can all be used as master nodes to send control bytes and transmit data to other nodes. However, if two or more nodes send a start signal to the bus and start transmitting data, a conflict will be formed. To resolve this conflict, an arbitration decision must be made, which is the arbitration on the I2C bus. The arbitration on the I2C bus

　　is divided into two parts: the synchronization of the SCL line and the arbitration of the SDA line. SCL synchronization is due to the fact that the bus has the logic function of line "AND", that is, as long as one node sends a low level, the bus will show a low level. When all nodes send a high level, the bus can show a high level. It is precisely because of the principle of the line "AND" logic function that when multiple nodes send clock signals at the same time, a unified clock signal is shown on the bus. This is the synchronization principle of SCL.

　　The arbitration of the SDA line is also based on the principle that the bus has the line "AND" logic function. After sending 1 bit of data, the node compares whether the data presented on the bus is consistent with the data sent by itself. If yes, continue to send; otherwise, exit the competition. Figure 3 shows the arbitration process of two nodes on the bus. The arbitration of the SDA line can ensure that the I2C bus system communicates normally and data is not lost when multiple master nodes attempt to control the bus at the same time. The bus system only allows one master node to continue to occupy the bus through arbitration [1].

　　Figure 3 shows the arbitration process of two nodes as an example. DATA1 and DATA2 are the data signals sent by the master node to the bus, SDA is the data signal presented on the bus, and SCL is the clock signal presented on the bus. When master nodes 1 and 2 send start signals at the same time, both master nodes send high-level signals. At this time, the signal presented on the bus is high-level. Both master nodes detect that the signal on the bus is the same as the signal they send, and continue to send data. In the second clock cycle, both master nodes send low-level signals. The signal presented on the bus is low-level, and they continue to send data. In the third clock cycle, master node 1 sends a high-level signal, while master node 2 sends a low-level signal. According to the logic function of the bus line "AND", the signal on the bus is low level. At this time, the master node 1 detects that the data on the bus is different from the data sent by itself, and disconnects the output stage of the data and switches to the slave receiving state. In this way, the master node 2 wins the bus, and the data is not lost, that is, the data on the bus is the same as the data sent by the master node 2, and the master node 1 continues to receive data after being converted to a slave node, and also does not lose the data on the SDA line. Therefore, no data is lost during the arbitration process.

Figure 3 Arbitration process of two master nodes

3 Principles of multi-master communication and its implementation process

　　Multi-master communication means that there are multiple nodes on the bus. These nodes can access other nodes as master nodes or be accessed by other nodes as slave nodes. When multiple nodes attempt to occupy the bus at the same time, bus arbitration is required. For the analog I2C bus system, how to implement bus arbitration is the difficulty in the current research on analog I2C bus system. Reference [4] proposes to add a BUSY line to the system and detect the BUSY line before occupying the bus to see if the bus is occupied. If the bus is idle, set the BUSY line and transmit data to the bus; otherwise, receive data until the bus is idle before occupying the bus. This method of implementing multi-master communication has two disadvantages: ① Because the biggest advantage of I2C is that it has fewer interfaces and high efficiency, doing so not only increases the use of resources but also reduces the advantages of the I2C bus; ② When the number of master nodes is relatively large, the waiting time is relatively long and the efficiency is not high. This design proposes an arbitration method based on delay comparison based on the arbitration principle of the bus. When the master node wants to occupy the bus, it first detects whether the bus is idle. If the bus is idle, it sends data. While sending data, the data on the bus is received and compared with the sent data. If they are different, it means that there are other nodes on the bus at the same time, so it exits; otherwise, it continues until the data is sent. This method not only reflects the efficiency of the I2C bus, but also has good scalability.

Figure 4 Multi-master communication process

　　Figure 4 shows the multi-master communication process based on delay comparison, in which the process of MCU as a slave node is given in Figure 5. Before the node sends the start signal, it is necessary to detect whether the bus is in an idle state (whether BUSY is 0). The detection method used here is to continuously detect whether the level on the bus is always high for a period of time. If it is, it means that the bus is in an idle state, otherwise it means that other nodes are using the bus and it is necessary to wait for a period of time before sending. When the bus is idle, send a start signal, and then send the address byte of the slave node to be accessed. Every time 1 bit of data is sent, it is received and compared once to see if the send and receive are consistent. If so, continue, otherwise jump out to the receiving state of the slave node. If there is no conflict, the MCU continues to send data as the master node until the task is completed, and then sends a stop signal and returns. If the data is different, the MCU will jump to the slave node state. Since the data of the accumulator (ACC) and the working register (Ri) have not changed in the process of jumping to the slave node receiving state, the data is not lost, and the slave node can continue to receive data on the bus. In this way, the entire communication process is not interrupted and the data is not lost. [page]

Figure 5 The process of the slave node

　　Figure 5 shows the process of the slave node. When entering the slave node, BUSY should be set to high, indicating that the MCU is working now and cannot complete other tasks. After the MCU completes the receiving task as a slave node, BUSY should be set to low. After receiving the address byte, the MCU compares it with its own address byte. If it is accessing itself, it will enter the following receiving program, otherwise it will jump out. When accessing itself, it is also necessary to determine whether the master node is reading or writing data in order to enter the corresponding program. In the subroutine of writing bytes, the slave node must check whether there is an acknowledgment signal (ACK) after sending each byte of data. If there is, it means that the data has been received; otherwise, it will jump out and wait and resend. In the subroutine of reading bytes, an acknowledgment signal (ACK) must be sent for each byte of data received to indicate that the reception is normal, otherwise the master node will stop sending. In the existing materials, there are relatively few principles and source codes about slave nodes. Here is the source code of the subroutine of writing bytes when acting as a slave node. Due to limited space, other subroutines are not listed.

4 Partial source code

　　This section is part of the source code in MCU multi-master communication. There are several difficulties and key points in the implementation of multi-master communication. The first is the subroutine for writing bytes when acting as a master node, which includes comparing each bit of data sent with the data on the bus and making a judgment. If the data is different, it is necessary to jump out and enter the state of the slave node. Since only the value of PC is changed when the subroutine returns to the master program, and the values ​​in the accumulator (ACC) and the working register (Ri) remain unchanged, the MCU continues to receive the remaining data on the bus after entering the slave state, so the data on the bus is not lost. The second is the subroutine for writing bytes when acting as a slave node. Since the clock line is controlled by the MCU of the master node, how to read the data on the SDA line according to the SCL line is one of the difficulties. The third is the judgment of whether the slave node with a subaddress is to write bytes or read bytes. If it is to write bytes, the master node will give a new start signal and send the address data of the slave node again. At this time, the slave node needs to make a judgment whether to read data or write data and enter the corresponding subroutine. Here are the source codes of the subroutines of the above three key points and difficulties for readers' reference. These source codes have been proven to be correct in practice.

　　The write byte subroutine of the master node:
;The NOP can be added or subtracted according to the speed of the clock
　　WRBYTE:MOV R0,#08H
　　　　　 CLR BUSY;Clear the BUSY value
　　WLP: RLC A;Get the data bit
　　JC WR1
　　　　　 SJMP WR0;Judge the data bit
　　WLP1: DJNZ R0,WLP
　　　 　　NOP
　　OUT1: RET
　　WR1: SETB SDA;Send 1
　　　 　　NOP
　　　 　　SETB SCL
　　　 　　MOV C,SDA;Judge whether it is the same as the sent data
　　 　　　JC GOON
　　　　 　SETB BUSY
　　　　　 AJMP OUT1
　　GOON: NOP NOP
　　　　　 NOP
　　　　　 CLR
　　　　　 SCL
　　　　　 SJMP WLP1
　　WR0: CLR SDA;Send 0
　　　　　 NOP
　　　　　 SCL
　　　　　 NOP
　　　　　 NOP
　　　　　 NOP
　　　　　 NOP
　　　　　 NOP
　　　　　 CLR
　　　　　 SCL
　　SJMP WLP1
　　The write byte subroutine of the slave node (return is ACK):
　　SWRBYTE:MOV R0,#08H
　　WAGAIN: RRC A
　　　　　　MOV B,#37H
　　WWAIT1: JB SCL,WWAIT1; wait for SCL to be low
　　　　　　JC WR1; determine whether to send "1" or "0"
　　　　　　SETB SDA; send "1"
　　　　　　AJMP COM
　　WR1: CLR SDA; send "0"
　　COM: DJNZ R0,WWAIT2; determine whether the sending is completed
　　WWAIT3: JNB SCL,WWAIT3; wait for the response signal after sending
　　WWAIT4: JB SCL,WWAIT4
　　WWAIT5: JNB SCL,WWAIT5
　　　　　　CLR ACK
　　　　　　JB SDA,ST0
　　　　　　SETB ACK
　　ST0: RET; return
　　WWAIT2: JNB SCL,WWAIT2; wait for SCL to be high
　　　　　　SJMP WAGAIN
　　　　　　reads the byte from the node and determines whether there is a start signal at the same time. If there is a start signal, switch to the write byte subroutine:
　　SRDBYTE:MOV R0,#08H
　　　　　　SETB 20H; set the flag to determine whether to read or write
　　　　　　SETB SDA; release the bus
　　RWAITJ: JNB SCL,RWAITJ; wait for SCL to be high
　　　　　　MOV C,SDA; read data from the bus
　　　　　　RRC A; store in accumulator
　　　　　　DEC R0
　　　　　　MOV C,ACC.7; determine whether it is a start signal
　　　　　　JNC RWAITJ1; continue to read data if it is low
　　REWAIT: JNB SCL,RWAITJ1; start to determine whether it is a start signal
　　　　　　JB SDA,REWAIT
　　　　　　CLR 20H; if yes, clear the flag and return
　　　　　　AJMP SjRDOUT
　　RWAITJ1:JB SCL,RWAITJ1; wait for SCL to be low
　　RWAITJ3:JNB SCL,RWAITJ3;Wait for SCL to be high
　　　　　　MOV C,SDA
　　　　　　RRC A
　　　　　　DJNZ R0,RWAITJ2
　　SjRDOUT:RET
　　RWAITJ2:JB SCL,RWAITJ2;Wait for SCL to be low and continue to read data
　　　　　　SJMP RWAITJ3

5 Summary

　　According to the arbitration principle in the bus protocol, the proposed method of simulating I2C multi-master communication based on delay comparison can not only reflect the high efficiency of the I2C bus, but also has good scalability. It enables ordinary MCUs without I2C interfaces to be used in multi-master communication systems, which not only increases the scope of use of ordinary MCUs, but also breaks through the application limitations of the simulated I2C bus, and plays a positive role in the promotion of the I2C bus.

References

1 The I2C-Bus Specification, Version 2.1. January, 2000. http://www.philips.com/
2 Zhang Kun, Qiu Yang, Liu Hao. Design of I2C bus in CPLD-based system. Electronic Technology Application, 2003 (11)
3 He Limin. Design of I2C bus application system. Beijing: Beijing University of Aeronautics and Astronautics Press, 1995
4 Zhang Dongmei, Fan Shibin, He Weimin. Universal software package for simulating I2C bus multi-master communication. Microcontroller and Embedded System Application, 2003 (12)