Application of I2C Bus in Multi-machine Communication

       I2C (Inter Integrated Circuit) bus is a bidirectional two-wire host bus developed by Philips, which can easily realize data transmission and control between chips. Through the two-wire buffer interface and internal control and status registers, non-master-slave communication or master-slave communication between multiple machines can be easily completed. The multi-machine communication circuit based on I2C bus has a simple structure, convenient program writing, and easy to realize the modularization and standardization of system hardware and software. 

       This paper gives a multi-machine communication dispatching and command system solution based on I2C bus, and discusses the software and hardware design of the system.

1 System hardware design 

       This dispatching and command system consists of two parts: the host and the dispatching console. The working principle is shown in Figure 1. The two use the RS422 bus to achieve long-distance data transmission. Both the host and the console use decentralized multi-processor control, and the processors use the I2C bus for data communication.

       The host adopts a decentralized control mode. The entire switching system is divided into multiple user subsystems and one communication subsystem. Each subsystem is responsible for call control and management of 128 users by a CPU processing unit. Multiple subsystems communicate with each other through I2C to form a masterless communication bus for information exchange (such as call processing information, maintenance information, etc.), forming a complete switching system. 

       The dispatch console is composed of the console control CPU, display screen and multiple user keypads, supporting 128 to 1024 operation buttons and 256 to 2048 LED indicators. Each operation button can be shortened to a group of telephone numbers corresponding to a telephone user in the host. The double light combination indicates the status of the telephone user and supports LCD Chinese display. The main control CPU inside the console and the user keypad control CPU form a master-slave communication bus through the I2CU call line to exchange information (button information, LED display information).

1.1 

       The CPU processing unit of the host I2C bus subsystem is composed of Philips-80C652 microcontroller and peripheral circuits (such as EPROM, RAM, EEPROM, decoding and I/O driver, etc.). 80C652 has an I2C bus serial interface that supports bidirectional data transmission. The I2C bus logic automatically transmits data according to the path. The CPU accesses the I2CU bus through the following four special function registers: 

       S1CON (D8H) SIO1 control register 

       S1STA (D9H) SIO1 status register 

       S1DAT (DAH) SIS1 data register 

       S1ADR (DBH) SIO1 slave address register 

       SIO1 logic is connected to the external I2C bus through the two pins P1.6/SCL and P1.7/SDA, and can work in the following four modes: master transmission mode, master reception mode, slave reception mode, and slave transmission mode. The I2C interface multiplexing between each subsystem constitutes the host I2C communication bus, which uses a masterless communication mode. Each CPU can respond to the broadcast call of the universal address or conduct point-to-point communication, which fully meets the information transmission requirements of program-controlled switching and has a simple structure. The connection diagram is shown in Figure 2.

1.2 I2C bus structure of the dispatching console 

       The control CPU board of the console is composed of Philips-80C652 single-chip microcomputer and peripheral circuits (such as EPROM, RAM, EEPROM, decoding and display drive circuits, etc.), and its P1.6-SCL and P1.7-SDA are I2C bus interface SIO1. The SIO1 of the single-chip microcomputer communicates with the host through the RS422 interface through MC3486/3487, and SIO1 communicates with the P87LPC764 of the user keyboard, which can support communication connections of up to 63 user keyboards. 

       Each user keyboard is controlled by the Philips-P87LPC764 single-chip microcomputer, and each chain board provides 64 user buttons and 128 user key lights. P87LPC764 is a 51LPC series OTP microcontroller. Its biggest feature is the improved 80C51 series. It adds a WDT watchdog, I2C bus, three analog comparators, and power-on reset detection to ensure that the I/O port drive current reaches 20mA, the operating speed is twice that of the standard 80C51, and the temperature range reaches the industrial standard (-40℃～+85℃). The I2C bus system of this chip includes an I2C bus hardware that simplifies software driving. In addition to the necessary bus arbitration, error detection, clock expansion and bus timeout timer, it includes a one-bit interface that synchronizes the software through cyclic query or interrupt. 

       The advantages of this design are strong system expandability and software function sharing: P87LPC764 performs key scanning and LED display processing, which greatly reduces the burden on the main CPU-80C652; due to the excellent cost performance of P87LPC764, it is cheaper than a dedicated keyboard circuit and its functions can be flexibly changed; the key board can be configured as needed, requiring only a simple 4-wire connection (SDA, SCL, +5V, GND). The schematic diagram of the I2C bus connection of the dispatching console is shown in Figure 3.

2 Data transmission mode of I2C bus 

       The serial data line SDA and serial clock line SCL communicate between I2C bus devices to transmit data and exchange information. Each device (microcontroller, LCD driver, memory or keyboard interface) must be set with a unique address code to distinguish it. According to the communication requirements, the device can work in sending or receiving mode, and multiple devices are allowed to control the bus as the master. The relationship between the master and slave, sending and receiving on the bus depends only on the direction of each data transmission. [page]

2.1 I2C bus transmission data format 

       The data transmission format of the I2C bus is shown in Figure 4. 

       S: start signal; 

       SLA: slave address, which can also be a universal address; 

       R/W: read and write control bit; 

       A: ACK response; 

       DATA0~DATA7: 8 data bytes are transmitted in each group; 

       S/P: the next start or stop signal. 

       First, send a start signal, and then transmit the first byte: the high 7 bits are the slave address, the low bits indicate the read/write (R/W) status, "0" indicates a write operation, and "1" indicates a read operation. Since the CPUs use masterless communication or master-slave communication, generally only the master send and slave receive modes are used, so the bit average value 0 indicates data transmission; each physical device on the bus determines whether the received address is consistent with the local address. If the addresses are consistent, ACK is returned for normal data transmission. Each address or data must be followed by an acknowledgment signal. When a normal acknowledgment signal is valid, the SCL clock is high, the receiving module data line SDA is set low, and data is transmitted byte by byte. The transmission is terminated by sending a stop signal or the next start signal. The 

       slave address is analyzed by each CPU according to a unified principle. The subsystems of the host can be arranged from 01H according to their own system numbers, and 00H is used as the general call address; the address of the dispatch station 80C652 is 01H, the address range of P87LPC764 is 40H~7FH, and other addresses are to be expanded. 

       The processors use a fixed 8-byte data communication: DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7.

DATA0: Destination address, the slave address can be determined according to this address when sending;

DATA1: Source address;

DATA2: Message code, which can be allocated as needed;

DATA3~DATA7: Other necessary information that the message should carry. 

       Taking the dispatch console as an example, 80C652 sends LED light display data to P86LPC764: destination address, source address, 55H (message code), key address, left light status, right light status, #0EEH, #0EEH.

Destination address: that is, P87LPC764 address, 40H~7FH;

source address: that is, 80C652 address, 01H;

key address: the key address processed by each P86LPC764, 00H~3FH (64 keys);

light status: that is, let the corresponding light be off, always on, flashing, etc. 

       Figure 5

3 Communication software design 

       When the host and dispatch station 80C652 microcontroller is powered on, the local slave address and general address are first loaded, and the I2C bus is set to high interrupt. The interrupt handler automatically receives data and stores it in the data buffer and checks whether there is data to be sent. If so, the corresponding sending information is sent, and the relevant processing is performed as required, and it is checked whether there is data to be sent. If so, it is filled in the sending buffer, and the S1CON flag to be sent is set, and the interrupt handler sends it. The process is shown in Figure 5. 

       The keyboard I2C bus software processing process is: the keyboard P87LPC764 is initialized, the local slave address is loaded, and the timer I is set to high interrupt and the PIC bus is interrupted normally. In the main program, the I2CU bus data transmission check is performed, and retransmission processing is performed; receiving data processing; processing of data to be sent and setting the master station to be sent. Timer I is responsible for monitoring the I2C bus, and the timer overflows to reset the I2C interface hardware. The I2C interrupt handler completes the data reception and transmission work. The process is shown in Figure 6. 

       This design uses the I2C bus to realize two-way communication between multiple modules in the dispatch command system. The circuit design is simple and easy to modularize and expand.