Design and implementation of HDLC protocol controller based on FPGA+ARM

Aiming at the communication requirements of HDLC protocol in flight control simulation device, a new HDLC protocol controller based on FPGA+ARM architecture is designed. The frame structure and cyclic redundancy check (CRC) principle of HDLC protocol are first introduced in this paper. Then, combined with the advantages of FPGA that can operate with any data width and ARM programming that is simple and flexible, the application method of frame structure and CRC check that conforms to HDLC protocol is effectively realized to meet the requirements of HDLC protocol. The application results show that the design can well meet the technical requirements of various functional indicators.

High-Level Data Link Control (HDLC) is a synchronous data transmission, bit-oriented data link layer protocol with powerful error detection function, high efficiency and synchronous transmission. At present, HDLC protocol has become one of the most widely used protocols in the communication field. In the field of aircraft design, it is often used as a communication protocol between flight control and steering gear, booster, etc. The

flight control simulator is used for flight control system software development and simulation evaluation in the scheme stage of aircraft development. Flight control software is often A-level software. Any problem in it will cause flight failure and then cause the paralysis of the entire system. Using an aircraft control system simulator to verify software algorithms, debug each subsystem software, and verify the system can speed up the aircraft design process and reduce design risks and costs. The

HDLC protocol controller studied in this paper is used for communication between the flight control simulator and the servo controller of a certain type of aircraft. Generally speaking, the HDLC protocol is mainly implemented by using dedicated chips and software programming. At present, there are many dedicated HDLC protocol processing chips on the market, such as MT8952B and MK5025. These chips have reliable performance but too strong functional targeting, and are suitable for mass production of specific purposes. The software programming method is to program the microcontroller or signal processor, but because the microcontroller or signal processor is based on byte (8-bit, 16-bit, etc.) processing, and the parsing and generation of the HDLC protocol frame is bit-oriented processing, this method will greatly increase the load of the microprocessor or signal processor. Considering that there are a large number of different bus interfaces that need to be processed in the flight control simulation device targeted in this design, its processor is FPGA+ARM. FPGA can process signals of any data width, and ARM has the advantages of simple programming and flexible modification. Therefore, this paper adopts the FPGA+AHM method on this basis to use FPGA to complete the data transmission control in accordance with the HDLC protocol, and ARM completes CRC check and information frame unpacking, and finally realizes the design of the HDLC protocol controller.

1 Introduction to HDLC protocol and CRC principle

HDLC is a high-level link layer control protocol and a bit-oriented data link layer protocol. HDLC is usually a point-to-point or point-to-multipoint structure, which can be used for half-duplex or full-duplex communication, and adopts synchronous transmission mode. It is often used in medium and high-speed data transmission occasions. HDLC uses a sliding window protocol, which can confirm several frames at the same time; in addition, each frame contains an address segment, so that in a multi-point structure, the master station can establish connections with multiple slave stations at the same time, and each slave station only receives frames containing its own station address. Therefore, the transmission efficiency of HDLC is relatively high and has a high throughput rate. In the HDLC protocol controller, the key to its implementation lies in two aspects. On the one hand, in order to ensure the uniqueness of the frame interval mark, the "0" bit insertion/deletion technology is used in the subsequent fields. When sending, all information other than the frame interval mark will automatically insert a "0" as long as there are 5 consecutive "1"s; similarly, when the receiver receives data, as long as it encounters 5 consecutive "1", it will automatically delete the "0" after it; on the other hand, the CRC code is generated and checked, that is, at the sending end, the CRC check code of a frame of data is automatically generated using the generating polynomial and attached to the information segment and sent out; at the receiving end, the CRC code is checked for the received frame of data. The

full name of CRC is Cvclic Redundancy Check, and its Chinese name is cyclic redundancy check. It is an important type of linear block code. The encoding and decoding methods are simple, and the error detection and correction capabilities are strong. It is widely used in the communication field to achieve error control. The basic principle is: for a given (N, K) code (K bits of information code followed by R bits of check code, N=R+K), it can be proved that there exists a polynomial C(x) with the highest power NK=R. Based on C(x), a check code for K bits of information can be generated, and G(x) is called the generator polynomial of this CRC code. The specific generation process of the check code is: assuming that the information to be sent is represented by the polynomial C(X), shift C(x) to the left by R bits (which can be represented as C(x)*2R), so that R bits will be vacant on the right side of C(x), which is the position of the check code. The remainder obtained by dividing C(x)*2R by the generator polynomial G(x) is the check code. According to the difference of R, a variety of different CRC standards are formed, such as (3RC-4: x4+x+1, CRC-8: x8+x6+X4+x3+X2+ X1, CRC16-CCITT: x16+X12+x5+1, etc. This paper adopts the CRC16-CCITT standard.

2 HDLC controller design

2.1 HDLC protocol processing circuit design

In order to meet the requirements of aircraft design verification, flexible configuration based on HDLC protocol transmission can be achieved. Its functions and technical indicators are as follows: 422 full-duplex; adjustable transmission rate, up to 2 Mbps; communication distance does not exceed 5 m; communication bit error rate is less than 10-7; frame header 7E and frame tail number are adjustable, and CRC check method adopts CCITT-CRC16. According to the functional and technical indicator requirements and the overall configuration of the flight control simulation device, the overall block diagram of the controller is shown in Figure 1.

Figure 1 Controller overall block diagram

The data processing unit is implemented by ARM, which completes the CRC check and information extraction of the data frame, and initializes the parameters of the transmission control unit according to the settings, including the baud rate and the number of valid 7Es; the transmission control unit is implemented by FPCA, and its main function is to realize the HDLC transmission control logic and data cache; the interface bus adopts the full-duplex RS422 data bus. Since the RS422 transmission line is a differential voltage, it is necessary to perform level conversion. Therefore, according to the design requirements, the controller designed in this paper uses MAX3491 as the electronic conversion chip, and its conversion speed reaches 10Mbps to meet the needs. This paper will focus on the data processing unit and output control logic for the HDLC controller design.

2.2 HDLC transmission control unit

HDLC transmission is a bit-by-bit operation, so it is completed by FPGA. The FPGA uses the CYCLONEⅡ series FPGA of Altera. The development platform is based on the QuartuslI 6.0 development environment. The transmission control part of the HDLC protocol is implemented by using the finite state machine design, and finally the design is implemented in the form of IP core, which is convenient for developers to maintain and upgrade.

Since the HDLC protocol controller is full-duplex communication, it includes the receiving circuit design of HDLC synchronous bit data and the sending circuit design of HDLC synchronous bit data frame. In the FPGA design, both the receiving end and the sending end are based on bit processing, and its functional block diagram is shown in Figure 2.

Figure 2 HDLC protocol controller transmission and reception function block diagram

At the receiving end, data is received according to the rising edge of the receiving clock RCLK signal. Before the information frame is sent, the frame header "7E" is judged and the number of "7E" is recorded. When the number of "7E" meets the setting requirements, the reception of the information frame is started and the counter is turned on. When 5 consecutive "1"s are encountered, the "0" after them is deleted. At the same time, serial-to-parallel conversion is performed, and the data is composed of 8BIT into one byte and stored in the FIFO. After the whole byte is received, if "7E" is received, it indicates that the information frame is over, and the number of "7E" is recorded. When the number of "7E" meets the setting requirements of the frame end, it indicates that the frame is received. Otherwise, it indicates that the reception is wrong and the frame is discarded. Figure 3 is the state transition diagram of the receiving frame.

Figure 3: Receive frame state transition diagram

At the transmitting end, after receiving the ARM start transmission instruction, the corresponding number of frame headers 0x7E are sent, and then the data is taken out from the transmission FIFO, and the parallel-to-serial conversion is performed. At the falling edge of the set clock TCLK, the data is sent bit by bit to the Tx line, and after sending 5 bits of "1" continuously, the bit "0" is automatically inserted. After the transmission is completed, the corresponding number of frame tails 0x7E are sent to end the transmission. The transmission frame state transition diagram is shown in Figure 4. [page]

Figure 4 Transition diagram of sending frame state

Figure 5 Data receiving flow chart of HDLC data processing unit

2.3 HDLC data processing unit

The HDLC data processing unit mainly completes the CRC check and packaging and unpacking tasks of the information frame. Its processing chip uses the STM32F103 series ARM chip of STMicroelectronics. The chip has the advantages of simple and flexible development and low cost. The data processing unit also includes two parts of receiving and sending. Taking receiving as an example, the specific workflow diagram is shown in Figure 5.

When entering the receiving interrupt process, the empty receiving FIFO is first read. The last two read data are the CRC check code of the frame information. The check code is used for CRC check. The check adopts the CRC-16-CCITT standard, and the generated r value is 16. The generating polynomial is: C (x) = x16 + x12 + x2 + 1. The traditional CRC check is to process the message bit by bit. For ARM, this efficiency is very low. In order to improve time efficiency, the usual idea is to trade space for time. Considering that the inner loop is only related to the current message byte and the low byte of crc_reg, a table is established for the low byte of crc_reg to query the corresponding CRC check code. If no error occurs after the final loop is completed, the result should be 0.

The sending unit is similar to the receiving unit. It is the reverse process. First, the information is packaged according to the agreed frame format, and then the CRC check is performed. The check code is placed in the last 2 bytes of the information frame, and the information frame is stored in the FPGA's send FIFO through the data bus. Finally, the send flag word is written to start the FPGA send transmission control logic.

3 Verification and results

To complete the design, ModelSim is first used for simulation verification. As shown in Figure 6, the read and write timing of ARM and FPCA is generated through the stimulus file, a set of data in accordance with the HDLC frame format is given and written into the FPGA send FIFO, and the transmission is started. In the stimulus file, RX/RCLK and TX/TCLK are shorted to form a loop. The FPGA receives the data according to the protocol controller and stores the data in the receive FIFO to complete the verification. Its logical timing meets the HDLC protocol frame format and communication timing requirements.

Figure 6 HDLC protocol controller ModelSim simulation verification diagram

Finally, according to the design requirements, the designed HDLC communication protocol controller is loaded onto FPGA and ARM, and a loopback test is performed with the serial communication card BST23109. The card can realize the serial port synchronization mode, and the communication meets the requirements of the HDLC protocol. The test results show that within a communication distance of 5 m, the baud rate can reach 2 Mb/s, and the bit error rate is 10-8.

4 Conclusion

This paper designs the HDLC protocol controller according to the application requirements of the HDLC protocol in the flight simulation device. This paper first introduces the relevant content of the HDLC protocol, and then focuses on the hardware and software implementation of the HDLC protocol controller, and gives the design and implementation process of the HDLC protocol controller in detail. Through simulation and actual testing, it is shown that within a communication distance of 5 m, the baud rate can reach 2 Mb/s, and the bit error rate is 10-8. During the delivery and use of the flight simulation device, the controller is fully functional and can well meet the technical requirements of various indicators.