Using ATmega32 microcontroller to configure FPGA

       Altera's ACEX, FLEX and other series of FPGA chips are widely used, but their FPGAs are based on SRAM structures, and the programming data that determines the logic functions of the circuits is stored in the SRAM.

       Due to the volatility of SRAM, the programming data must be reloaded into SRAM every time the power is turned on. This process is the configuration process of FPGA. The configuration of FPGA is divided into active and passive. In active mode, after the FPGA is powered on, it actively loads the configuration data from the dedicated EPROM (such as EPC1, EPC2, etc.) into SRAM. In passive mode, the FPGA is a slave device, and the configuration process is controlled by the corresponding control circuit or microprocessor, including computer-controlled configuration through a download cable and microcontroller simulation configuration timing configuration. Among them, the dedicated EPROM is expensive and has a small number of programmable times, and computer configuration is not realistic in field applications. Therefore, this article proposes a passive configuration method based on AVR microcontrollers. Since the capacity of the embedded flash memory of the AVR series microcontrollers is 8 to 128kB, it can accommodate the configuration files of small and medium-sized (less than 100,000 gates) FPGAs and configure them. In addition, multi-task configuration can be realized. The following will take FLEX10K10 as an example to introduce the dual-task configuration of FPGA by microcontrollers.

       ATmega series microcontroller

       ATMEL's ATmega series microcontrollers are divided into ATmega8, ATmega32, ATmega128, etc. according to the size of the on-chip flash memory. This design uses ATmega32, which contains 16K×16 32KB of on-chip programmable ROM, which can be erased and written 10,000 times, can load the configuration data of FPGA within 20,000 gates, and has a maximum performance of 16MIPS, which can complete the configuration of FPGA in the shortest time. If you need to configure an FPGA with a higher number of gates, you can use MEGA128.

       Hardware circuit design

       ATmega32 contains 32KB of flash memory, and the FPGA is FLEX10K10, whose configuration file size is 15KB, so this solution can realize dual-task configuration. In terms of hardware connection, when using the microcontroller configuration mode, MESL0, MESL1, and nCE of FLEX10K10 must be grounded, and nCONFIG, DCLK, DATA0, nSTATUS, and CONF_DONE must be connected to PA0~PA4 of MEGA32 respectively. The I/O ports of MEGA32 are all programmable. PA0, PA1, and PA2 are set as output ports, and PA3 and PA4 are set as input ports as needed. In addition, two buttons need to be connected to PB0 and PB1 of the microcontroller to select the configuration task. The specific circuit is shown in Figure 1.

Figure 1 Hardware block diagram

       Configuration

       The configuration methods of Altera's FPGA devices mainly include AS (active serial method), PS (passive serial method), PPS (passive parallel synchronous method), PPA (passive parallel method) and JTAG (boundary scan method). Using a single-chip microcomputer to configure the FPGA mainly adopts the single-chip microcomputer to simulate the timing of the PS method to realize the configuration of the FPGA device.

       The working process of the passive serial mode is as follows: five pins are required for configuration, among which nCONFIG, DCLK, and DATA0 are the output pins of the microcontroller, and nSTATUS and CONF_DONE are the input pins of the microcontroller. After the system is powered on, the microcontroller generates a negative pulse greater than 8μs on nCONFIG. After the FPGA detects the falling edge of nCONFIG, it will start the configuration process, and nSTATUS and CONF_DONE will be pulled low. Within 1μs after nCONFIG is raised, nSTATUS is raised, and the configuration data is sent from low to high on DATA0 in sequence. When all the configuration data are sent, CONF_DONE is raised. When the MCU detects this change, the configuration process ends. Subsequently, DCLK must provide several cycles of clock (10 cycles for FLEX10K) for the FPGA to correctly complete the initialization and enter the user mode. If the configuration process fails, nSTATUS will be pulled low and the MCU will restart the configuration process. Its configuration timing is shown in Figure 2.

Figure 2 Passive serial configuration timing diagram [page]

       Configuration Files

       Altera's development tools Quartus II and MAXPlus II can generate a variety of configuration files, including sof, pof, hex, rbf, ttf, etc. This configuration scheme uses the rbf file, which is a binary file that contains all the configuration data. One byte of rbf data contains 8 bits of configuration data. During configuration, the lowest bit is loaded first from the lowest bit to the highest bit.

       Software Design

       The key to designing FPGA using a single-chip microcomputer is software design. In a dual-task configuration, the configuration data of the two tasks are stored in continuous memory areas with different starting addresses. After the single-chip microcomputer is powered on and reset, it enters the key query state. After detecting that a key is pressed, the single-chip microcomputer reads data from the corresponding starting address and configures the FPGA. The configuration process is carried out according to the timing requirements of the PS mode, and after the configuration is completed, it re-enters the key query state. The control program flow chart is shown in Figure 3.

Figure 3 Control program flow chart

       In dual-task configuration, the configuration data of the two tasks are stored in the specified addresses respectively, and the boot program reads the data from the specified addresses and configures the FPGA. The merging of the boot program and the rbf file (configuration data) is the key to software design, and its processing is detailed below.

       (1) Compile the bootloader under ICCAVR and generate mcu.hex. The hex file format is defined by Intel. It is data information arranged by address. The data width is bytes. All data is represented by hexadecimal numbers. The following is an example.

       :10008000AF5 F67F0602703E0322CFA92007780C361

       :1000900089001C6B7EA7CA9200 FE10D2AA00477D81

       :0B00A00080FA92006F3600 C3A00076CB

       :00000001FF

       In the first line, the ":" symbol indicates the start of the record. The next two characters indicate the length of the record, which is 10h here. The next four characters give the address to be loaded, which is 0080h here. The next two characters indicate the type of record, followed by the actual data record, the last two characters are the checksum check, and the last line is the end string. It is always written like this;

       (2) Change fpga1.rbf to fpga1.bin, and use the "Super MCU Tool" to convert fpga1.bin into fpga1.hex with a starting address of 0x0273 (the data length of mcu.hex);

       (3) Change fpga2.rbf to fpga1.bin, and use the "Super MCU Tool" to convert fpga2.bin to fpga2.hex with a starting address of 0x3bd7 (the sum of the data lengths of mcu.hex and fpga1.hex);

       (4) After deleting the end string, merge mcu.hex, fpga1.hex and fpga2.hex into config.hex in sequence;

       (5) Download config.hex to the ATmega32 microcontroller using a download cable.

       in conclusion

       The above solution is applicable to FPGA configuration of 3.3V and 5V systems, without the need to expand EEPROM, and can also realize multi-task configuration.