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【Perf-V Evaluation】+ Construction and basic use of development environment (2) [Copy link]

This post was last edited by jinglixixi on 2021-1-22 18:08

2. Basic usage of Windows-IDE

1) Open Perf-V IDE, that is, double-click the icon

on the desktop to enter the working interface.

2) To create a new project, click the "New Project" button on the left side of the toolbar, as shown in Figure 12.

Figure 12 New construction project

3) In the interface shown in Figure 13, fill in the project name test, select Perf-V C Project, and then click "Next".

Figure 13 Setting project options

4) In the interface shown in Figure 14, check "Debug" and "Release", then click "Next" and "Finish" in sequence to complete the creation of the new project.

Figure 14 Configuration selection

Figure 15 Toolchain settings

Figure 16 Complete project creation

5) Write code. You can write code directly in the test.c file of the project, or you can add a new c file to the newly created project or directly copy the existing c file to the project.

Figure 17 Program Editing

6) Compile and run. Click the Build icon on the toolbar to compile. The compilation result is shown in Figure 18.

Figure 18 Compilation results

7) To run the program, right-click the launch file in the project and select "1 test-debug-openocd" under "Run As" in the shortcut menu, as shown in Figure 19.

Figure 19 Running the program

Under normal circumstances, the execution results can be observed. But for some reason, when the compilation is normal, two different prompts will often appear (see Figure 20 and Figure 21). Perhaps this is related to the problem after installing the driver!

Figure 20 Abnormal phenomenon 1

Figure 21 Abnormal phenomenon 2

I hope someone who knows the reason can give me some advice to solve this problem. Thanks in advance.

This post is from FPGA/CPLD

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Open "Details" and take a screenshot. You can see that this IDE is modified from Eclipse. This kind of IDE usually has a "Run Configure" configuration. You can also take a screenshot. Generally, OCD problems are caused by changing this.  Details Published on 2021-1-25 20:18
 

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Open "Details" and take a screenshot. You can see that this IDE is modified from Eclipse. This kind of IDE usually has a "Run Configure" configuration. You can also take a screenshot. Generally, OCD problems are caused by changing this.
This post is from FPGA/CPLD
 
 

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This post was last edited by jinglixixi on 2021-1-26 10:00
Ansersion published on 2021-1-25 20:18 Open "Details" and take a screenshot. You can see that this IDE is modified from Eclipse. This kind of IDE usually has a "Run Configure" configuration. You may...

The screenshots are as follows:

In addition, the prompts for running are as follows:

Open On-Chip Debugger 0.10.0+dev-gdd0dd7f64e03-dirty (2018-01-09-17:24)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
Error: Trying to use configured scan chain anyway...
Error: IR capture error at bit 5, saw 0x51 not 0x...3
Warn : Bypassing JTAG setup events due to errors
Info : Exposing additional CSR 3040
Info : Exposing additional CSR 3041
Info : Exposing additional CSR 3042
Info : Exposing additional CSR 3043
Info : Exposing additional CSR 3044
Info : Exposing additional CSR 3045
Info : Exposing additional CSR 3046
Info : Exposing additional CSR 3047
Info : Exposing additional CSR 3048
Info : Exposing additional CSR 3049
Info : Exposing additional CSR 3050
Info : Exposing additional CSR 3051
Info : Exposing additional CSR 3052
Info : Exposing additional CSR 3053
Info : Exposing additional CSR 3054
Info : Exposing additional CSR 3055
Info : Exposing additional CSR 3056
Info : Exposing additional CSR 3057
Info : Exposing additional CSR 3058
Info : Exposing additional CSR 3059
Info : Exposing additional CSR 3060
Info : Exposing additional CSR 3061
Info : Exposing additional CSR 3062
Info : Exposing additional CSR 3063
Info : Exposing additional CSR 3064
Info : Exposing additional CSR 3065
Info : Exposing additional CSR 3066
Info : Exposing additional CSR 3067
Info : Exposing additional CSR 3068
Info : Exposing additional CSR 3069
Info : Exposing additional CSR 3070
Info : Exposing additional CSR 3071
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

I hope you can give me some advice, thank you!

This post is from FPGA/CPLD
 
 
 

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