my country breaks through trench silicon carbide MOSFET chip manufacturing technology for the first time

On September 3, the official WeChat account of "Nanjing Release" published a blog post on September 1, reporting that the National Third Generation Semiconductor Technology Innovation Center (Nanjing) has successfully tackled the key technology of trench silicon carbide MOSFET chip manufacturing after 4 years of independent research and development, breaking the performance "ceiling" of planar silicon carbide MOSFET chips and achieving my country's first breakthrough in this field.

Project Background

Silicon carbide is one of the main representatives of the third-generation semiconductor materials, with excellent properties such as wide bandgap, high critical breakdown electric field, high electron saturation mobility and high thermal conductivity.

Silicon carbide MOS mainly has two structures: planar structure and trench structure. Currently, the industry's main applications are planar silicon carbide MOSFET chips.

The characteristics of planar silicon carbide MOS structure are simple process, good cell consistency and high avalanche energy; the disadvantage is that when the current is confined to the narrow N region close to the P body region, a JFET effect will be generated when the current flows through, increasing the on-state resistance and large parasitic capacitance.

Planar and Trench SiC MOSFET Technology Comparison

The trench structure buries the gate into the substrate to form a vertical channel. Its characteristics are that it can increase the cell density, has no JFET effect, and the channel crystal plane can achieve the best channel mobility. The on-resistance is significantly lower than that of the planar structure. The disadvantage is that due to the need to open the trench, the process is more complicated, the consistency of the cell is poor, and the avalanche energy is relatively low.

The trench gate structure design has obvious performance advantages over the planar gate structure, which can achieve lower conduction loss, better switching performance, and higher wafer density, thereby greatly reducing the cost of chip use. However, it has been limited by the manufacturing process, and trench silicon carbide MOSFET chip products have been slow to come out and be used.

Project Introduction

Huang Runhua, technical director of the National Third Generation Semiconductor Technology Innovation Center (Nanjing), said that "the key lies in the process." Silicon carbide material has a very high hardness. Changing the plane into grooves means "digging holes" in the material, and the "dig" cannot be "bumpy."

National Third Generation Semiconductor Technology Innovation Center (Nanjing). Image source: Jiangning Release.

During the preparation process, the etching accuracy, etching damage and etching surface residues of the etching process have a fatal impact on the development and performance of silicon carbide devices.

The National Third Generation Semiconductor Technology Innovation Center (Nanjing) organized a core R&D team and a full-line cooperation team, which took 4 years to continuously try new technologies and eventually established a new process flow, overcoming the difficulties of "digging holes", stability, and accuracy, and successfully manufactured trench silicon carbide MOSFET chips.

The conduction performance is improved by about 30% compared with the planar type. Currently, the center is developing trench silicon carbide MOSFET chip products and launching trench silicon carbide power devices, which are expected to be put into use in new energy vehicle electric drive, smart grid, photovoltaic energy storage and other fields within a year.

Project Significance

What impact will it have on people’s lives? Huang Runhua took new energy vehicles as an example and said that silicon carbide power devices have the advantage of saving power compared to silicon devices, which can improve the endurance by about 5%. After applying the trench structure, a lower resistance design can be achieved.

When the conduction performance index remains unchanged, a higher density chip layout can be achieved, thereby reducing the cost of chip use.