Towards domain-specific EDA

It appears that more and more companies are creating custom EDA tools, but it is unclear whether this trend is accelerating and what it means for the mainstream EDA industry.

Wherever there is change, there is opportunity. Change can come from new abstractions, new optimization options, or new constraints imposed on tools or processes. For example, the slowdown of Moore's Law means that sufficient performance, power, or cost improvements cannot be made between specific versions of a product simply by moving to the next node. The design itself must be improved, or the product must be redesigned.

One change that is starting to make its way into design methodology is the move away from static tools and toward dynamic tools. Static tools will look at a design and optimize it independently of any specific use case or scenario. Dynamic optimization adds one or more scenarios as inputs to the optimization process, allowing the tool to perform more targeted optimizations. This started with power optimization when performing clock or power gating, which used to be static operations. These techniques can be further improved by understanding exactly how and when various parts of the design need to be active. This is also driving a resurgence in processor design, where custom processors can be created that are best suited for specific tasks.

Semiconductor companies have always created some of their own EDA tools. “In the 80s, most semiconductor and ASIC companies had their own tools,” says Simon Davidmann, founder and CEO of Imperas Software. “But then resource issues arose, and customers wanted a more standardized approach. The industry moved from proprietary solutions for design and semiconductor companies to one that was standards-driven, trying to build universal solutions that work for everyone.”

There’s also room for some specialized tools. “Every design company has some design or data management problem that’s proprietary to them,” said Rob Aitken, technology strategist at Synopsys. “Sometimes, after they’ve created a solution, they don’t want their competitors to get it, so they keep it in-house. They may have concluded that this is the only way to solve it, and there may be a number of reasons, but ultimately a more broadly applicable EDA solution may be useful to them.”

Tools are always in a state of flux. “The EDA business has to have a large enough market to justify the investment in tools,” said Neil Hand, director of technology strategy for design verification at Siemens EDA. “When it comes to solutions for a specific industry, a specific application, or a specific domain, what really limits this is how generalizable the problem is. And then the second part is the language or functionality that encapsulates that generalization.”

Some domains are large enough to support specialized solutions. “Domain-specific things are nothing new,” said Tom Feist, an embedded entrepreneur and contractor at openROAD. “The FPGA industry is one example, and EDA and academia are responding to this challenge with solutions that include MATLAB, OpenCL, C/C++, Python, and Simulink-based designs. Using National Instruments’ LabVIEW is another example.”

There is always a balance between specificity and flexibility. “Domain-specific systems encounter an interesting overlap of technical and economic issues,” says Duaine Pryor, an EDA technology consultant. “When you make them general enough to win a market that justifies leading edge development, they lose the value of the technical advantage gained through specialization. Of course, the reverse is also true. This propagates throughout the value chain.”

Market and industry dynamics change. “There are companies that have a lot of resources at the forefront of their field, trying to find ways to go further than EDA companies can,” said Imperas’ Davidmann. “That’s why some companies are acquired by semiconductor companies, where they chew and spit as a way to gain expertise in-house. I’m sure Apple’s success with M1 and M2 is because they have so many tools in-house.”

Anyone working with the latest nodes knows the pressures they face. “As semiconductor scaling slows or fails, architectural innovation and domain-specific optimizations are needed,” said Zdeněk Přikryl, CTO at Codasip. “Increasing the level of abstraction and efficient design automation can speed up design cycles and thus reduce time to market.”

In addition, many new technologies are being inserted into the design flow. “Whenever you start talking about new technology, such as photonics, you may find a gap between what’s available and what’s needed,” said Jeff Roane, product manager at Cadence. “But once there’s a need, that gap closes quickly to the point where it makes financial sense for one of the big players to develop something.”

Building the necessary expertise will take time. "The quantum EDA field must cross the barrier between physics and engineering," said Mohamed Hassan, head of quantum solutions planning at Keysight Technologies. "This is a difficult task. The two fields often use different terminology and nomenclature. Currently, the quantum hardware design cycle spans multiple tools from multiple domains in a jarring way, with multiple gaps between them that are often filled by additional efforts that are highly dependent on the designer's knowledge and experience."

Electronic system-level work in the late 1990s was an attempt to introduce new abstractions and new languages. “It started out broadly and ended up targeting only datapath-centric and similar algorithmically simple designs,” said Synopsys’ Aitken.

For some of the tools developed as part of that flow, the market does continue to grow and evolve. “System-level coprocessor hardware/software co-design and optimization is really starting to look more like a true disruption, but it has a real ‘back to the future’ flavor,” Pryor said. “The industry initially ran into this problem when many systems — especially cell phones — were getting more heterogeneous compute architectures. Some good solutions emerged, but they became niche products due to a combination of economics and engineering silos. The last 20 years of optimized design, high-level synthesis, domain-specific languages, and other developments have probably made this area more tractable than it was a millennium ago.”

ESL is also being influenced by the growing IP market. “Today we see the concept of tools plus IP,” said Cadence’s Roane. “You’re seeing processor IP, memory IP, interconnect IP, interface IP, and even algorithmic content that’s covered in high-level synthesis today. But if you look at the types of designs that are really suited to high-level synthesis, it’s algorithmic design. The whole concept of tools plus IP is already in play today, and you’re going to see more of it.”

Virtual prototyping brings its many parts together. “Domain-specific EDA might help generate virtual prototypes of parts of it, like a processor or other component used in an SoC,” says Codasip’s Přikryl. So on one hand, domain-specific EDA is enabled by virtual prototyping, where each vertical is significantly accelerated and optimized with dedicated flows tailored to those functions. If I draw a parallel with the software world, we can write code in multiple languages ​​and glue everything together in a linker. It’s the same in the hardware world. We just use different integration approaches.”

As abstractions are raised, workloads become more important. “Years ago, you could optimize for power in placement, and that’s all people could really do,” said Siemens’ Hand. “Then power became part of synthesis and implementation tradeoffs. Then it became part of high-level synthesis tradeoffs. Now it’s part of processor optimization tradeoffs, and we’ll continue to move forward and it will become part of system-level tradeoffs.”

These workloads are driving design practices. “Hyperscalers are doing chip designs because their specific workloads are unique and different from the workloads their vendors are trying to target,” Roane added. “You can use off-the-shelf processors to do these tasks, but you’ll pay a high price in terms of power consumption. You may not get the best performance compared to a custom implementation. We see a lot of hyperscalers doing chip designs today because they’re trying to reduce power consumption and increase performance for specific workloads that are unique to them.”

Machine learning is also creating some unique flows. “We’re seeing a lot of domain-specific architectural languages ​​being created,” Aitken said. “When you think about it from an EDA perspective, there’s definitely an opportunity for some custom design methodologies, starting with the language you use to describe these things. How does a synthesis flow optimized for a specific architecture differ from the synthesis flows that exist today? How do you customize an algorithm that will produce custom blocks?”

In the past, many domain-specific tools came from startups. “They see an opportunity where customers are asking for something that EDA can’t meet,” Davidmann said. “We’re moving from simulation companies to verification because of the demand that RISC-V is creating and the need for a processor verification ecosystem. There are a few companies that are building solutions because customers want them, but the big EDA companies haven’t done that yet. Smaller companies are creating that, and there will be consolidation over time.”

This has also fueled interest in open source EDA. “One compelling reason to use open source is the ability to modify the tool to their specific needs,” says openROAD’s Feist. “That could be for security or to take advantage of features like machine learning. Google has been a big supporter of open source, and it’s not because the tools are too expensive for them. It’s because they want a competitive advantage, and if they give the secret sauce to EDA vendors, then everyone has it.”

efabless has put together such an open source process (shown in Figure 1).