Moore's Law Now and in the Future

The essence of Moore's Law is innovation, and we can confidently say that innovation will never stop.

summary:

Intel has been relentlessly advancing Moore's Law and has a deep foundation in basic innovation in process technology.

Advanced packaging provides architects and designers with new tools in the process of advancing Moore’s Law .

Intel has a complete research system, which gives us the confidence to continue Moore's Law.

In summary, designers and architects have many options when it comes to fulfilling the mission of Moore's Law.

Written by: Ann Kelleher, PhD

Executive Vice President and General Manager of Technology Development, Intel

introduction

Figure 1: Original image from the article "Putting More Components on an Integrated Circuit"1

In 1965, Gordon Moore, co-founder of Intel, predicted that the number of transistors on a single chip would double approximately every two years with only a minimal increase in cost. This prediction became known as Moore’s Law, as shown in Figure 1. The more transistors or components on a single device, the lower the cost of the device while increasing its performance.

Under the influence of the COVID-19 pandemic, the world's digitalization has accelerated dramatically in the past two years, and the semiconductor industry and its innovations have intensified the digitalization process.

Intel CEO Pat Gelsinger said: "Technology has never been more important to humanity. Everything is being digitized, driven by four super powers." These four super powers are ubiquitous computing, cloud-to-edge infrastructure, ubiquitous connectivity, and artificial intelligence, which will transcend and change the world. Currently, we see that the world's demand for computing power is endless, and more computing power will continue to drive more innovation in the industry. For example, the world generates about 270,000 PB (27 x1019) of data every day. It is expected that by 2030, the average person will have 1 petaflop (1015 floating-point operations per second) of computing power and 1 PB of data, with a latency of less than 1 millisecond. This increasing demand for computing power is the driving force behind the industry to advance Moore's Law.

For more than 40 years, Intel engineers have continued to innovate, integrating more and more transistors onto smaller chips, and continuing to advance Moore's Law. In the mid-to-late 2010s, the industry repeatedly predicted that "Moore's Law is dead", and I think such reports are exaggerated. Innovation has not stopped, and Intel will continue to advance Moore's Law through innovations in process technology, packaging and architecture. Challenges always exist, and Intel is ready to face them.

Innovation today

Process ​

Figure 2: Transistor innovation over time

As shown in Figure 2, Intel has a deep heritage in fundamental innovations in process technology as it continues to advance Moore's Law. As features on chips shrink to the atomic level, Intel engineers and scientists continue to face and overcome the challenges of physics. With inventions such as high-k metal gate technology, tri-gate 3D transistors, and strained silicon, Intel continues to deliver breakthrough technologies to advance Moore's Law. By the late 2000s, as physical dimensions continued to shrink, the industry realized that innovations in other areas were needed to keep up with Moore's Law, including materials science, new process architectures, and design-process co-optimization (DTCO).

Intel's next great architectural innovation is RibbonFET, Intel's implementation of Gate All Around (GAA) transistors, which will be launched with Intel 20A. RibbonFET represents Intel's first new transistor architecture since FinFET. RibbonFET can provide faster transistor switching speeds with the same drive current in a smaller footprint. At the same time, Intel also provides the industry's first back-side power transmission architecture PowerVia. Previously, power came from the top of the die and "competed" with signal interconnects. Now by separating power and signals, metal layers can be used more efficiently, which reduces the trade-off between the two and improves performance. The next generation of extreme ultraviolet (EUV) lithography technology, namely high numerical aperture (High-NA), further improves resolution and reduces errors, reduces the complexity of process technology, and increases the flexibility of design rules. Intel is working closely with ASML and other ecosystem partners to take the lead in putting this technology into mass production.

These examples are just the beginning. Following the introduction of RibbonFET and PowerVia at the Intel 20A and Intel 18A nodes, new subsequent process nodes are already in development with further optimizations for power, performance, and density. These advances are enabled by multiple innovations, including improvements in back-end metal resistance and capacitance, transistor architecture, and library architecture. As Intel implements these and other innovations, we expect to be on par with the industry in transistor performance per watt by 2024 and lead by 2025, as Intel announced in July 2021.

Packaging ​

Figure 3: Packaging innovation over time

The role of packaging and its contribution to Moore’s Law scaling is evolving. Until the 2010s, the primary role of packaging was to carry power and signals between the motherboard and the chip and to protect the chip. From wire bonding and leadframe packaging, to flip-chip technology on ceramic substrates, to the adoption of organic substrates and the introduction of multi-chip packaging, each evolution at that time increased the number of connections. These connections enable more functionality in the chip, which is also required for Moore’s Law scaling. Packaging is the vehicle for realizing the benefits of Moore’s Law. (See Figure 3.)

Looking ahead, as we enter the era of advanced packaging, we see packaging bringing improvements in transistor density. Even Gordon himself recognized the importance of packaging and wrote in his original paper: "It may prove more economical to build large systems out of smaller functional blocks that are packaged and interconnected separately." As we enter the era of advanced packaging, these 2D and 3D stacking technologies provide architects and designers with the tools to further increase the number of transistors in a single device and will help achieve the scaling required by Moore's Law.

Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, for example, allows designers to “pack more transistors” into a package (as Gordon puts it), far exceeding the size limitations of a single die. EMIB technology also enables the use of chips from different process nodes in a single package, allowing designers to choose the best process node for a particular IP. Intel’s Foveros technology offers the industry’s first active logic die stacking capability, which adds logic transistors in three dimensions. Both achievements represent a significant change in how Intel is approaching fitting more and more transistors into a single package. Combined, these technologies enable unprecedented levels of integration. For example, with Ponte Vecchio, Intel combines 47 different die in a single package, setting a new benchmark for advanced packaging capabilities.

Intel's upcoming next-generation Foveros technologies, Foveros Omni and Foveros Direct, offer new scaling, new interconnect technologies, and new mix-and-match capabilities. Foveros Omni further scales the interconnect pitch to 25 microns and adds the option of multiple base wafers, achieving nearly 4 times the density improvement compared to EMIB technology, while also expanding Intel's ability to mix and match base wafers. Foveros Direct introduces solderless direct copper-to-copper bonding, enabling low-resistance interconnects and bump pitches below 10 microns. The resulting interconnect capabilities open up new horizons for functional die partitioning, which was not possible before. At the same time, the technology can also vertically stack multiple active layers of chips. As these and other technologies enter the market, advanced packaging will provide designers and architects with another tool to advance Moore's Law.

Future innovations

Component research

Figure 4: Main research areas of Intel's component research team

As I mentioned earlier, I believe that innovation, as well as the needs of end users, drives the advancement of Moore's Law. Intel's component research team focuses on three key research areas (shown in Figure 4) to provide the foundational building blocks for more powerful computing in the future. Intel has a complete research system, which gives us the confidence to continue to advance Moore's Law for the next decade or more. Future innovations that advance Moore's Law are limited only by our imagination. Recently, at the 2021 IEEE International Electron Devices Meeting (IEDM), Intel outlined several areas of future innovation.

One of the focuses of Intel’s research efforts is scaling technologies that provide more transistors in the same area. This includes innovations in lithography, such as Directed Self-Assembly (DSA), to improve edge roughness and increase edge positioning accuracy. We are also investigating new materials that are only a few atoms thick to make thinner transistors, thereby reducing their overall size. In addition to innovations like this, Intel is creating feasible technologies to stack transistors vertically, either monolithically integrated on the same chip or, like chiplets, by using advanced packaging technologies such as hybrid bonding to continuously reduce the vertical interface spacing. With the freedom provided by new materials, transistor architecture innovations, lithography breakthroughs and packaging inventions, designers are only limited by their imagination.