At the forefront of technology, TSMC is moving into 1nm process

Most of the semiconductors we use now are silicon-based circuits, which have been around for 60 years. For many years, they have been developing in accordance with Moore's Law, which is a two-year miniaturization rule, but it has its limits after all. After TSMC has broken through 5nm, 3nm and the future 2nm, the next step is to move into 1nm technology.

According to TSMC's plan, the 5nm process will be mass-produced this year, and the 3nm process will be mass-produced in 2022. The 2nm process is already under development and is expected to be released in 2024.

What comes after 2nm? TSMC also stated at a recent shareholders meeting that it is researching processes below 2nm and is gradually approaching 1nm.

The 1nm process is not only important because of the number, it also has a deeper meaning - the 1nm level process may be the end of silicon-based semiconductors. Going further will require changing materials, such as nanosheets, carbon nanotubes, etc. In 2017, a scientific research team led by IBM successfully used carbon nanotubes to manufacture 1nm transistors.

The limits of silicon-based semiconductor technology have actually been constantly being broken. In the past, 10nm, 7nm, 5nm, 3nm and even 2nm were all considered to be the limits of silicon-based technology. Now it seems that they are being broken through step by step, if we don’t consider the marketing tricks used by TSMC and Samsung in naming their processes.

At the 2019 Hotchips conference, TSMC's head of R&D and vice general manager of technology research Philip Wong talked about the limits of semiconductor processing in his speech. He believes that by 2050, transistors will reach the hydrogen atom scale, that is, 0.1nm.

Regarding the future technology route, Huang Hansen believes that carbon nanotubes (1.2nm scale) and two-dimensional layered materials can make transistors faster and smaller; at the same time, phase change memory (PRAM), rotational torque transfer random access memory (STT-RAM), etc. will be directly packaged with the processor to reduce the size and speed up data transmission; in addition, there is 3D stacking packaging technology.