【AT-START-F403A Review】4. Try 3 ADC synchronous triggering + AN11 simplified code

mig29

【AT-START-F403A Review】4. Try 3 ADC synchronous triggering + AN11 simplified code [Copy link]

 

When I wrote the evaluation application, I mentioned that I was going to test the ADC performance of these domestic MCUs. According to the results of another company tested earlier, the performance should be in line with the specifications.
So for Arteli, the focus was on the unique "3 ADCs", but unfortunately I didn't understand how they were triggered synchronously (this application is to trigger and convert 3 ADCs at the same time. To achieve this goal, ADC1 and ADC2 use dual ADC mode (synchronous rule group mode), and ADC3 uses the same trigger source as ADC1 and ADC2 to achieve synchronization.)

In terms of performance, there are several ADC-related articles on Arterytek's official website, such as this one:
http://atkap.arterytek.com/download/FAQ0025_ADC_sampling_result_at_4MHz_CH_V1.0.0.pdf
(The AT32F403 ADC was tested at a 4 MHz sampling rate, and the result was worse than the upper limit of 2 MHz in the data sheet. The overall resolution is guaranteed to be 12 bits at a sampling rate of 2 MHz, and about 9.2 bits at 4 MHz.)

There are three codes for the three ADCs:
1. 3ADCs_DMA in AT32F4xx_StdPeriph_Lib_V1.2.4.zip
2. SC0001_Timer triggers 3 ADCs to sample a specified number of times simultaneously
3. AN0011: How to trigger 3 ADC conversions through the same trigger source

I tested the third one. There were some problems with the original project configuration. The attached version has been modified and simplified (the CMSIS library not used in this demo has been deleted).

AN11_3ADC_Simultaneous_Trigger_by_EEW_mig29.rar (1.6 MB, downloads: 6)

2020-11-30 22:49 上传

点击文件名下载附件

Wiring diagram:
LQFP100:
pin23 = PA0 = ADC123_IN0 = J2.23 Peripheral
pin24 = PA1 = ADC123_IN1
pin25 = PA2 = ADC123_IN2
pin26 = PA3 = ADC123_IN3
pin29 = PA4 = ADC12_IN4
pin30 = PA5 = ADC12_IN5
pin31 = PA6 = ADC12_IN6

Measured results:
When PA1/2/3 are all connected to Gnd:
DMA1_Enter_IRQ
ADC1_Channel1_Value = 0x023
ADC2_Channel2_Value = 0x01F
DMA2_Enter_IRQ
ADC3_Channel3_Value = 0x01B

When PA1/2/3 are all connected to Vdd:
DMA1_Enter_IRQ
ADC1_Channel1_Value = 0xFA5
ADC2_Channel2_Value = 0xFAD
DMA2_Enter_IRQ
ADC3_Channel3_Value = 0xF9D

Judging from this result, there should be something wrong with the results connected to Gnd and Vdd, but I haven't figured out the problem of "synchronous triggering" yet, so I won't delve into the measurement results for now.

freebsder

Are they three hold sampling circuits or one circuit with polling multiplexing?