Design of Multi-channel SSI Communication Controller Based on FPGA

Using VHDL hardware description language and Xilinx FPGA as the design platform, the control unit with open source soft core MC8051 as the core is designed to control the SoPC architecture communication controller of 4-way SSI protocol modules, and the communication controller is functionally simulated and verified. The controller can flexibly expand the IP core module, and can be used as a peripheral processor to interconnect and communicate with TI's TMS320C6000 series DSP, separating the slow serial communication tasks, thereby reducing the burden on the DSP and improving the overall performance of the system.

In the field of embedded system applications, the tasks that need to be completed are becoming more and more complex, and the application environment is becoming more and more harsh, requiring embedded computers to have stronger processing capabilities and lower power consumption while their size is constantly decreasing. This paper adopts FPGA[1] design technology and uses VHDL hardware description language[2] to combine four synchronous serial interface protocol SSI IP core[3] modules into a function-scalable SoPC architecture slave communication controller, so that the master and slave controllers can work together, ensuring that the entire embedded system can more effectively reduce system power consumption and size while meeting technical requirements for communication speed.

1 SoPC Design Methodology

System on Programmable Chip (SoPC) (or single-chip system based on large-scale FPGA) is a flexible and efficient SoC solution. It integrates the functional modules required by the system, such as processor, memory, I/O port, etc., into a PLD device to form a programmable system on chip. It has a flexible design method (can be cut, expanded, and upgraded) and has the function of in-system programmability of software and hardware.

Figure 1 shows a typical SoPC design flow based on IP core library, which mainly uses the software-hardware collaborative method to complete the entire system design.

2 Communication Controller Architecture Module Composition

This paper adopts a new SoPC architecture. The entire embedded system is mainly composed of two functional units: the master controller and the FPGA (slave controller). Its structure is shown in Figure 2. The master controller uses TI's TMS320C6713 DSP, and the circuit unit in the virtual box is the designed multi-channel synchronous communication controller (also known as the slave controller). Data is exchanged with the multi-channel synchronous communication controller based on FPGA through the EMIF module of the TMS320C6713 processor chip. The FPGA-based slave processor uses the MC8051 IP soft core to control and manage the 4-way SSI protocol communication controller. TMS320C6713 and MC8051 share data and exchange information through dual-port RAM. The entire system uses interrupt control to realize the collaborative processing of master/slave controllers.

As shown in Figure 2, the SoPC architecture controller can be divided into four modules: the MC8051 IP core, the 4-way SSI protocol communication controller, the dual-port RAM and the interrupt logic unit. The following introduces the four main modules.

2.1 From the processor

In order to improve the autonomy and flexibility of the synchronous communication controller, a microcontroller 80C51 IP core is embedded in the FPGA as the core control unit of the synchronous communication controller. The main features of the MC8051 IP soft core are: the instruction set is compatible with the industrial standard 8051 controller; the new architecture increases the processing speed of the microcontroller by 10 times; there is no multiplexing I/O port, and the input and output interfaces are completely isolated; 256 B of internal RAM; up to 64 KB of internal ROM and up to 64 KB of external RAM; easy to adjust or change the VHDL source code to achieve related core expansion functions; parameterization can be performed through VHDL constants.

Figure 3 is the internal functional structure diagram of the MC8051 IP core. As can be seen from the figure, the submodules of the IP core are: arithmetic logic unit MC8051_ALU, serial interface unit MC8051_SIU, timer/counter unit MC8051_TMRCTR, core control unit MC8051_CONTROL, internal data storage unit MC8051_RAM, internal program storage unit MC8051_ROM and external data storage unit MC8051_RAMX. Among them, N represents the number of MC8051_SIU and MC8051_TMRCTR units that can be flexibly set according to actual needs. Its range is 1 to 256, which can be set by changing the value of parameter C_IMPL_N_TMR in the VHDL code.

2.2 SSI protocol controller

The synchronous serial interface (SSI) [4] communication protocol is a type of synchronous serial communication protocol. The protocol mainly includes three types of signals: frame synchronization signal GATE, clock signal CLK and serial data DATA. The timing relationship between them is shown in Figure 4.

In Figure 4, the frame synchronization signal GATE has two optional modes, Mode 1 and Mode 2, to coordinate the control of the clock signal CLK and the serial data DATA. Mode 1 is represented by the dotted curve ①. In this mode, when the entire system is idle, GATE is always in a high-level state. When a transient low-level pulse is triggered, DATA is transmitted at the rising edge of the GATE signal according to the system configuration requirements, and GATE remains high. Mode 2 is represented by the solid curve ②. In this mode, when the system is idle, GATE is always in a low-level state. When a transient high-level pulse is triggered, DATA is transmitted at the falling edge of the GATE signal, and GATE remains low. In the above two modes, DATA can remain stable and be collected at the rising or falling edge of CLK.

The SSI IP core interface signal diagram is shown in Figure 5.

This paper defines 4 channels (A~D) of SSI IP core with the same structure. MC8051 controls the data receiving/transmitting operations of the 4-channel communication protocol controller through interrupt and query mode.

2.3 Dual-Port RAM

The storage space of the external data memory MC8051_XRAM in MC8051 can reach up to 64 KB. This design uses VHDL language to generate a 32 KB external data expansion dual-port memory MC8051_XRAM, one end for MC8051 IP core operation, the other end for DSP operation, through address line decoding, thus providing MC8051_XRAM and 4-way SSI protocol controller with chip select signals such as cs_x and cs_a~cs_d. The address line input to the MC8051_XRAM module is addra (15:0), and the address line space actually used is addra (14:0), supporting 32 KB addressing space.

2.4 Interrupt Logic Unit

The operation address of the interrupt logic unit is FFD3H. When the DSP writes to this address, the interrupt logic unit will send a low-effective interrupt signal to the multi-channel synchronous communication controller; when the MC8051 in the multi-channel synchronous communication controller writes to this address, the interrupt logic unit will clear the interrupt. The signal interface information of the interrupt logic unit is shown in Table 1.

Select channel A to simulate the transmission of parallel data, and the test simulation is shown in Figure 7. As can be seen from the figure, under the action of MC8051 working clock Wr_clk and external frequency-divided clock Exclk, the parallel data Data is transmitted by setting the register combination in channel A to achieve the final serial data transmission. Therefore, it can be verified that the data transmission simulation function is correct.

Select channel B to simulate the reception of peripheral serial data, and the test simulation is shown in Figure 8. As can be seen from the figure, under the action of MC8051 working clock Clk and external frequency division clock Exclk, serial data Rxd is received by configuring the register combination in channel B to obtain parallel data. Therefore, it can be verified that the data reception simulation function is correct.

This paper takes Xilinx's FPGA device as the design platform and adopts VHDL hardware description language to design a slave communication controller of SoPC architecture. The design scheme is simulated and verified, and the correctness of the design scheme is obtained. It has been successfully used in a telemetry data engineering practice. It is easy to promote and use because of its high data transmission rate, portability of IP core and flexible scalability.