Powering FPGAs with LM201xx PowerWise® Synchronous Buck Regulators

The LM201xx PowerWise® synchronous buck regulators are feature-rich devices that deliver up to 5A of continuous output current. The devices operate from an input voltage range of 2.95V to 5.5V and can convert output voltages as low as 0.8V. Integrated low source-drain on-resistance (RDSON) FETs provide a very efficient power solution for the multiple power rails required by FPGAs. All devices operate in current mode, provide excellent line regulation and load transient response, and require only two external compensation components. Features include precision enable, soft-start, tracking, undervoltage lockout (UVLO), overvoltage protection (OVP), overtemperature protection, and power good signal (PGOOD). A capacitor and soft-start pin can be used to control startup inrush current, or an external voltage source can be used to track or sequence multiple power supplies. All devices enter a preset output state without discharging, and all devices have a diode emulation mode for higher efficiency at light loads. Devices in the family are distinguished by output current capability (3A, 4A, and 5A), operating frequency (500 kHz, 1 MHz, and 1.5 MHz), and synchronization modes (free-running, sync-in, sync-out, and external resistor adjustment). Depending on the power requirements of the FPGA design, the devices can be appropriately combined to produce a small, efficient, and complete solution.

FPGA Power Requirements

There are several high-performance FPGAs on the market today, such as Xilinx's Virtex and Spartan series, and Altera's Cyclone and Stratix series. These devices require multiple power rails, including the FPGA core, I/O, and additional power rails for clocks, PLLs, transceivers, and other circuits. The core voltage of current FPGAs can be as low as 0.9V, and the current requirements for this power rail depend greatly on the FPGA application. FPGA manufacturers provide power estimation software to help users determine their power requirements based on the performance requirements of the design. The I/O power rails also have demanding power requirements, which depend on the number of I/O registers used in the FPGA design. Most of the latest FPGAs have built-in POR circuits that can eliminate the need for power rail sequencing. When selecting an FPGA, determine the input inrush current for a specific power-up sequence, while others require sequencing of rail voltages to avoid startup issues or latch-up failures. The startup time required for FPGA power rails varies from 100-200 us as fast as possible to 50-100 ms as slow as possible.