Application of FPGA in Information Processor of Missile

introduction

The information processor (Figure 1) is used to complete the collection, processing, and packetization of multi-channel telemetry information on the missile. The main functions include data transmission and reception of the high-speed 1553B bus, data loading and detection of 422 interface devices, multi-channel data fusion, and data reception, processing, and packetization and transmission. Among them, the bus data and the data sent from other 422 interfaces are processed in parallel at the same time; the input information of each channel is fused and output according to the predetermined format; the data output rate is based on the frame synchronization pulse of the high-speed synchronous 422 port. If the high-speed synchronous 422 port is abnormal, it will not affect the bus data and the data fusion and output function of other 422 ports. When the CPU is abnormal or the bus data is abnormal, it will not affect the fusion and output function of the data of other 422 ports; it can perform secondary screening and packetization on the data received from the bus, and send it to the bus for other devices to receive.

Figure 1 Information Processor Functional Block Diagram Pop-up Functional Block Diagram

System Design

CPU Selection

The data collection of 4M 1553B bus is managed by the 4M bus intelligent communication interface, received and packaged by the CPU, and then returned to the 4M bus and sent to the FPGA for collection. The CPU uses Atmel's AT91FR40162S, which has 256KB of internal SRAM and 2M x 8b FLASH memory, and the main frequency can reach up to 75MHz. The waiting circuit of the ARM is generated by the hardware waiting logic and implemented inside the FPGA. The main external interrupt sources of ARM are: 4M 1553B communication controller interrupt; 20ms buffer switching interrupt. Among them, the 4M 1553B communication controller interrupt signal is sent to the ARM after being shaped by the FPGA. The 20ms buffer switching interrupt is provided to the framing state machines of each synchronous and asynchronous communication IP inside the FPGA for buffer switching.

3-way digital input interface

There are three digital input channels with bit rates of 1.28Mbps, 115.2Kbps and 38.4Kbps respectively. The data streams are converted from serial to parallel inside the FPGA and the received data are stored in data buffer A and data buffer B. The data are then continuously updated through the state controller.

Synchronous 422 interface output

It uses two unidirectional RS422 synchronous serial communication interfaces, differential transmission, one for serial data and one for clock data, and two-wire transmission. The output code rate is 2.56Mbps, with 15-bit scrambling.

FPGA Design

When 3 digital input data streams and 4M 1553 data are transmitted within 20ms, the required memory is about 10KB.

There are two ways to switch buffer storage:

1) Switch when the number of data received by the 1.28M synchronous serial interface reaches 64x100;

2) Switched by an internal 20ms timer.

Therefore, when ARM is abnormal, it can ensure the normal output of other channels except 4M bus data. When the 1.28M synchronous serial interface is abnormal, the state machine in the FPGA automatically switches to the internal 20ms timer for switching. The FPGA design and IP core are simulated and verified by SPARTAN3AN integrated development environment.

The FPGA uses Xilinx's SPARTAN3AN series XC3S700AN-4FG484, with a voltage of 1.2~3.3V, a current of 50mA~2A, and a main frequency of up to 70MHz.

Design of Ground Unit Tester

The unit tester (Figure 2) is mainly used to test various functions and parameters of the information processor, simulate the generation of all input signals on the missile machine, and test all its output signals. It can be used for production debugging, factory testing and external factory maintenance of the information processor.

Figure 2 Block diagram of ground unit tester

The unit tester consists of a portable industrial computer with a corresponding PCI board and corresponding software program inserted in it. The PCI board is a COM communication test board, which mainly realizes the interface with the high-speed internal bus 4Mbps (or above) 1553B bus on the missile. Under the control of the software, it sends various test commands to the missile and receives the test results from the missile computer.

System Implementation

The system workflow of the information processor is shown in Figure 3, which specifically includes:

(1) Power-on reset and initialization

After power-on, the FPGA and ARM are reset at the same time and the initialization process is carried out. During the FPGA initialization, the initial values ​​of the FPGA internal registers and logic states and the internal buffer data are cleared by the reset signal. The "FPGA parameter setting" is executed by the monitoring program or completed by the FPGA using default parameters.

If a problem occurs during power-on or reset, the FPGA automatically initializes all parameters using default parameters and automatically performs subsequent operations.

(2) 20ms buffer switching signal synchronization

After initialization, the "20ms buffer switching signal" inside the FPGA generates logic and automatically executes the synchronization process with the "1.28M synchronous input serial port". No data is sent out during the synchronization process. Once synchronized, the synchronization lock signal Sync Locked = "1" will be given, and data collection work for all channels will start, entering the telemetry information receiving process.

(3) Telemetry information reception

The data acquisition of the channels uses the "20ms buffer switching signal SwitchBuf" generated inside the FPGA as a 20ms period mark to switch the buffer (dual port), which are A and B buffers.

The 1.28M channel should complete the reception of 32x100=3200 Bytes of data within 20ms and invert the current SwitchBuf signal according to the word counter.

The 4M 1553B channel should be completed by ARM to receive, filter and pack the telemetry data of the 4M 1553B bus, forming a telemetry data packet of about 1500 Bytes within 20ms and filling it into the packet buffer allocated to it. The FPGA automatically generates the corresponding packet length information and puts it into a packet length FIFO. After that, ARM restarts the next 20ms data reception work, and the cycle repeats. During the framing process, once the framing state machine (MFSTM) finds that the packet length FIFO is not empty, it reads the data packet of the corresponding length from the packet buffer FIFO and fills it into the data fusion table according to the specified format and position.

Figure 3 Information Processing Machine Workflow

The 38.4K asynchronous serial input channel is completed by the FPGA's UART IP core to receive the serial input data. The IP core determines whether a frame is received based on whether the word interval exceeds the receiving time of 2 words. The principle is the same as the reception of 1553 bus data.

The 115.2K asynchronous serial input channel is completed by the FPGA's UART IP core to receive serial input data. The buffer consists of a FIFO. The framing state machine will query the FIFO empty and full status at any time. If it is not empty, it will start the continuous reading process, reading a data from the FIFO every 200μs and filling it into the data fusion table according to the specified format and position until the data of the FIFO is taken out. If it is empty, the position data of the corresponding channel of the new frame is filled with zero.

(4) Framing

Framing is the data fusion of telemetry data. It organizes each channel of telemetry information into a complete 100-frame format (1 frame 200us, 100 frames 20ms) for transmission according to a given data fusion format. This function is completed by the "framing state machine (MFSTM) IP" designed inside the FPGA.

(5) Data fusion table

After power-on reset, the framing state machine MFSTM waits for the synchronization lock signal Sync Locked = "1" before starting to work, and switches periodically according to the 20ms buffer switching signal SwitchBuf. According to the sequence designed in the data fusion table, the 1.28M synchronous input serial port buffer, 4M 1553B bus data buffer, 115.2K asynchronous input serial port buffer, 38.4K asynchronous input serial port buffer, etc. are accessed in sequence, and the specified amount of data is read and filled into the 20ms data fusion table in sequence, and repeated 100 times, thereby completing the filling of rows 1 to 100 in the table. The data structure of the data fusion table is designed as FIFO. Using FIFO can balance the speed difference between the fast framing state machine and the slow sending state machine, so that the sent data stream is kept below the baud rate of 2.56Mbps and continuously sent.

(6) Send

The sending of the data fusion table is completed by the "Send State Machine (SendSTM) IP". It takes the data fusion table FIFO and 2.56M sending clock as input, and once started, it will not stop. The sending state machine first queries the data fusion table FIFO. If the FIFO is empty, it waits; if the FIFO is not empty, it continuously reads the data of the data fusion table FIFO at a fixed clock frequency of 2.56M/8, and then sends it to the "15-segment scrambler" for scrambling. The scrambled data and clock are converted into RS-422 differential form by the RS-422 driver circuit and sent to the encryptor, that is, 2.56M output.

(7) 1.28M synchronous input serial port fault detection

The fault detection unit (FDU) in the FPGA is responsible for detecting whether the input signal of the 1.28M synchronous input serial port is normal. When the fault detection unit FDU finds that the error between the period of the SwitchBuf signal generated by the 1.28M synchronous input serial port and the 20ms clock period generated by the crystal oscillator exceeds △T (such as ±2ms), it is considered that the 1.28M synchronous input serial port is faulty and the SwitchBuf signal is immediately switched to the 20ms clock generated by the crystal oscillator.

System Simulation

The following is the simulation of the main functions of the system by related software:

Figure 4 FPGA resource utilization after ISE compilation

Figure 5 Simulation results of data fusion table

The structure of the data fusion table is 100 rows and 64 columns. Columns 1-32 are high-speed synchronous interface data, columns 33-50 are bus data, columns 51 and 52 are 115.2K and 38.4K interface data respectively, and there are also a small amount of analog data, full frame counts, synchronous code groups, etc.

Figure 6 Comparison of data fusion table input and output

Since the framing speed is much faster than the reading speed, it is displayed in two graphs.

Figure 7 2.56M sending data

Conclusion

FPGA is used to replace conventional processors to realize the collection, fusion and real-time transmission of multi-channel data. The rich programmable logic resources and internal memory of FPGA are used for logic design, which greatly reduces the types and quantity of peripheral components and improves the system's processing and I/O bandwidth.

At the same time, the application of FPGA in the aerospace field has also promoted the development of programmable technology.