FPGA Implementation of New Data Format Conversion

introduction

Floating-point operations are one of the most common operations in digital signal processing. All major EDA software come with free floating-point operation IP cores. By generating and instantiating IP cores to achieve floating-point operations, FPGA designers are freed from the heavy code writing. At the same time, the IP core can be functionally tailored to avoid wasting FPGA logic resources and achieve optimal design. However, little attention has been paid to the acquisition of floating-point numbers. In floating-point operations, single-precision floating points have been the most widely used due to their strong versatility. This article focuses on the acquisition of single-precision floating-point numbers to provide a data source for floating-point IP cores. In data transmission, ASCII code is a frequently used form. This article takes the real number represented by the ASCII code received by the serial port as an example and uses pipeline processing to convert the real number into a single-precision floating point number at high speed.

1 Principle of converting real numbers to single-precision floating-point numbers

1.1 Single-precision floating point format

The representation of floating point numbers follows the IEEE 754 standard, which consists of three parts: the sign bit (sign), the exponent (exponent), and the mantissa (fraction). The single-precision floating point format specified by the IEEE 754 standard occupies 32 bits, including: 1 sign bit s, 8-bit exponent e[30:23] with offset, and 23-bit mantissa f[22:0], as shown in Figure 1. The single-precision exponent is represented in the form of a positive bias value, and the exponent value ranges from 1 to 254 (0 and 255 are special values). This form of representation is used to facilitate comparison of sizes. When calculating floating point decimals, the exponent value minus the positive bias value is the actual exponent size. The bias value is 127, and the mantissa has 1 hidden bit.

Single-precision floating-point numbers include the following:

(1) Normalization number: 0

(2)(+0, -0): If e=0 and f=0, then V=(-1)s×0;

(3) Non-normalized number: if e=0 but f≠0, then V is a non-normalized number;

(4) (+∞, -∞): e = 255, and f = 0, then V = (-1)s × ∞;

(5)NaN (not a number): e=255 and f≠0, then V=NaN.

1.2 Conversion Principle

For example, if there is a real number of 6.91, first convert it to binary form: 110.1110100011110101110000101000. Then normalize it as follows:

6.91=1.101110100011110101110000101000×22, we can get the basic prototype:

s:0;

e: 2+127(decimal)=129(decimal)=10000001(binary);

f: 101110100011110101110000101000 (Note: the decimal part is 28 digits, and the 1 in front of the decimal point is omitted).

The purpose of taking 28 bits for the decimal part is to more accurately represent the real number, and the last five bits are used for rounding. In the IEEE 754 standard, four optional methods are provided for rounding: rounding to the nearest, rounding to 0, rounding to +∞, and rounding to -∞. This article adopts the principle of rounding to the nearest. The essence of rounding to the nearest is what is commonly called "rounding". For example: the extra digits exceeding the specified 23 digits are 10010, and the value of the extra digits exceeds half of the specified minimum effective value. Therefore, the least significant digit should be increased by 1. If the extra 5 digits are 01111, simply truncate. For the special case of the extra 5 digits 100 00: if the least significant digit is 0, truncate; if the least significant digit is 1, carry one digit up to make it 0. Therefore, in this example, the last 5 digits should be discarded. The result is: 0 100000011011101000111101011100001. The combination is 0100 0000 1101 1101 0001 1110 1011 1000, which is equal to 40DDIEB8. In principle, the conversion from a real number to a single-precision floating point number is completed.

2. The process of implementing real number to single-precision floating point conversion in FPGA

2.1 Conversion Process

In actual engineering applications, the data processed has a range that is larger or smaller. Converting real numbers to single-precision floating-point numbers within this range will save chip resources and reduce power consumption. Therefore, the conversion of real numbers to single-precision floating-point numbers is completed within the range of -9 999.999 9 to 9 999.999 9, as shown in Figure 2. Considering the actual situation, the values ​​are often obtained through the serial port and are expressed in ASCII form. Therefore, the real numbers mentioned in this article are all expressed in ASCII.

The conversion process uses pipeline operation and uses a counter to control the conversion process. The method of converting ASCII code to single-precision floating point is as follows:

(1) Convert the digital characters represented by the 8-bit ASCII code into decimal numbers (since the hardware circuit can only represent numbers in the combination of 0 and 1, the integer and decimal of the real number are represented separately);

(2) Use the data type conversion function in the package to convert the decimal number to binary, but the conversion of the decimal part needs to be implemented separately;

(3) Normalize the real numbers represented in binary format;

(4) Determine the sign bit s according to the ASCII code value of the sign bit, determine the exponent e according to the number of bits shifted by the normalization, and retain 28 bits of the decimal part f in the normalization;

(5) Determine and round the last 5 digits of the retained 28-digit decimal part according to the principle of rounding to the nearest integer.

2.2 Key code analysis

In the hardware description language of FPGA, it is relatively simple to convert the decimal integer to binary. It can be implemented by calling the conversion function in the program package of ISE software. However, how to convert the decimal part to binary is the key to whether the conversion from real number to single-precision floating point number can be successfully completed. Considering the need to round the decimal part, the decimal part is converted to 28-bit binary. To represent the decimal part with 28-bit binary, it is necessary to use the feature of the variable in VHDL language that takes effect immediately when it is assigned a value, combined with the FOR loop to implement it. Some key codes are as follows:

In the code, frac_part is the decimal representation of the fractional part (because the integer type can only represent integers, the fractional part is enlarged by 10,000 times, but it does not affect the correctness of the result), and frac_28 is the binary representation of the fractional part. The weight of the signal frac_28(27) is 2-1, which decreases by 1/2 in turn, and the weight of frac_28(0) is 2-28. This process is started by the change of frac_part, and the time to complete the conversion is instantaneous, which can also be considered as one clock cycle.

3 Simulation results and analysis

First, use ModelSim to perform functional simulation, and the results are shown in Figure 3. The input real number is 125.763, and the output result is compared with the input value through Matlab reverse evaluation to verify the correctness of the conversion result. The correct conversion of a number does not explain the problem, and the feasibility of this conversion method will be verified below.

Representative real numbers are selected to verify the performance of the conversion method. The main verification is in two aspects:

(1) Whether it has full coverage within the predetermined area;

(2) Whether the minimum value in this domain can be effectively represented.

The results are shown in Table 1.

According to the conversion principle, the conversion error of the minimum value is the largest, but the conversion error of the maximum value is not necessarily the smallest (because of rounding). This maximum conversion error is in the order of 10-5. When the absolute value of the real number to be converted is greater than the integer 1, the conversion error will be less than 10-5 and can reach 10-9. Such a conversion error can meet the accuracy requirements of most floating-point computing environments. Experiments have verified the effectiveness and "full coverage" of this conversion method.

After completing the simulation test, the program is synthesized, laid out and wired, and finally the bitstream file is generated and downloaded to the FPGA chip for verification. In the actual chip, the conversion result is compared with the simulated result, and the indication signal is output. From the actual circuit output result, it is completely consistent with the simulation result, which proves the feasibility of this method in the actual chip. Because pipeline operation is adopted, the number of cycles used in the simulation is consistent with the actual number of cycles. The experiment takes 6 cycles (i.e. 0.12μs) to complete the conversion operation under the 50 MHz clock. Under the most commonly used serial port transmission baud rate of 9600 b/s, the time to transmit one code element is on the order of 10-1ms. It can be concluded that the time used to complete the conversion from the real number represented by the ASCII code (-9999.9999～+9999.99999) to the single-precision floating point will be less than 10-1μs, which has high real-time performance.

4 Conclusion

The conversion to single-precision floating point in this paper takes up 1,161 slice resources, which is acceptable in most applications as FPGA capacity and resources have greatly improved. The design in this paper can be easily adjusted to the range of actual real numbers and can be extended to other floating-point formats, effectively providing a fast and high-precision data source for floating-point IP cores.