A path to transistor miniaturization using engineered substrates

The continued miniaturization of transistors has an extraordinary impact on our daily lives. Back in 1997, IBM built a giant supercomputer called Deep Blue, which weighed 1.4 tons and had a computing power of 11.38 GFLOPS. Deep Blue defeated the famous Russian chess grandmaster Garry Kasparov in a six-game chess tournament. Today, the computing power of Deep Blue can be realized in a smartphone. For example, the A5 processor used in the iPhone 4S has a computing power of 16 GFLOPS. In 2011, IBM's Watson supercomputer, which consists of 10 racks of IBM Power 750 servers, equipped with 15TB of random access memory (RAM) and 2,880 processors, has a total computing power of 80 TFLOPS and defeated the two best champions of the show "Jeopardy". Can you imagine that in 10 years, the mobile devices in our hands will have the same computing power? This is not a fantasy, but the progress depends heavily on the efforts to miniaturize transistors based on the realization of Moore's Law.
 

Scaling involves two major tasks: making transistors smaller to reduce cost/function and improve performance and power consumption. Historically, people have been able to achieve both density and performance goals at each new technology node. In the process of process development to 32nm node technology, people have successfully and accurately achieved the goals of shrinking the integrated circuit area and doubling the transistor density at the same time in each generation of technology. However, people still often need to make trade-offs between factors such as performance, power consumption and density/area. Engineers have also shown amazing creativity in developing solutions to bridge the generational gap.

At present, people have made some breakthroughs in overcoming these technological limits. In terms of materials, one of the major improvements is the improvement brought about by the introduction of High-K materials for the miniaturization of gate insulation layers. The introduction of strain can improve the mobility of carriers and offset the limited gain caused by the reduction of gate oxide and gate length. In terms of power, the speed of supply voltage reduction lags far behind the planned value required by miniaturization theory. Therefore, multi-core processors, multi-threshold voltage (multi-Vt), and complex power management strategies have emerged. Today, lithography technology is increasingly becoming a hindrance to breaking through technological limitations. Extreme ultraviolet technology (EUV) and the use of 193nm wavelength technology in 28nm and below processes have been postponed, giving rise to immersion lithography and multiple lithography technology, which is known as double patterning. It is foreseeable that the adoption of triple patterning technology will be inevitable at the 14nm node.

It is people's continuous innovation that makes various products follow Moore's Law and keep moving forward. The history of miniaturization technology is a history of innovation, not a simple repetition. The recent major breakthrough in 22nm nanotechnology is Intel's 3D device architecture. This fully demonstrates that fully depleted transistors can improve integrated circuit performance and/or reduce power consumption by integrating more transistors in the same area, which is an excellent solution.
 

The structural difference between a fully depleted transistor and a traditional transistor is that the channel of the former is not defined by its doping level, but by its physical dimensions, and the boundaries are composed of oxide materials. The uniqueness of this structure in design improves the gate control of the channel, improves performance and shortens the length of the gate. In addition, since the channel definition is no longer limited by the doping level of the channel, fully depleted technology provides another option, that is, using an undoped channel. This can reduce variability and improve carrier mobility. Under current electronic technology conditions, channel doping is the main source of variability, and increasing carrier mobility will increase the drive current and increase the operating frequency.

It is generally accepted that fully depleted transistors can be used up to the 10nm node with acceptable electrostatic performance (down to 7nm), so the technology can continue to drive scaling until 2020.

There are currently two fully depleted transistor structures that can be realized: FinFET and fully depleted planar transistor technology (FD-SOI). FinFET can be manufactured on either SOI or bulk substrates.

Figure 1. 3D and planar fully depleted transistors on SOI: (left) FinFET on Soitec FD-3D substrate, fin height defined by silicon layer thickness; (right) planar FD-SOI transistor on Soitec FD-2D substrate, channel thickness defined by silicon layer thickness

FinFET architecture has been proven to meet the needs of high performance/low power consumption at a micronized size. However, FinFET requires a quantized circuit design, and each transistor can only have a limited number of fins. In planar design, people can use transistors of different sizes (from tens of nanometers to micrometers), but on FinFET, only one or several fins can be selected. Currently, the design is limited by the repeated exposure required by lithography to obtain precise printing effects. It is precisely because lithography is the main technical limitation under current technical conditions that the quantization of FinFET is not the main design obstacle. However, once the lithography technology improves (such as the expected introduction of EUV technology), this small design impact will be transformed into a huge advantage of the former over the latter in the process of planar FD-SOI technology versus FinFET technology.

All fully depleted structures are very sensitive to the channel structure, especially when the channel is undoped. In this regard, SOI substrates can bring unique and extremely low physical variability - Figure 2 shows that the consistency error of SOI substrates is less than 0.5nm, and mass production has been achieved. In the case of FinFET, FD-3D substrates not only ensure excellent fin height reproducibility, but also ensure an efficient fin definition process, which is greatly simplified compared with similar bulk designs. In the case of FD-SOI, FD-2D substrates can even achieve those technologies with the most stringent requirements for thickness control. Compared with FinFET, planar FD-SOI can achieve good power consumption optimization that dynamically adapts to the applied substrate bias. In addition, the doped ground plane under the buried oxide layer also provides an effective option for multi-threshold voltage management.

Figure 2: Thickness measurement of 300mm substrate silicon wafer

Figure 2 shows the consistency of thickness of Soitec's advanced substrates, with an error of less than 0.5nm. The current production line is able to produce substrates with various dots, and all wafers have an error control range of +/- 0.5nm. These substrates have enabled further miniaturization of CMOS in the fully depleted era.