What does 4-wire I2C have more than 2-wire I2C?

The figure below shows the structure diagram of RT1052 low-power I2C.

You can see that the box placed above it is the host part, which is mainly composed of FIFO, configuration register, host logic module, prescaler and error filter.

The slave is composed of sending data, receiving data/address, configuration register, slave logic module, and error filter.

Clocks include functional clocks, external clocks, and bus clocks.

①Functional clock.

It is the root clock LPI2C_CLK_ROOT of LPI2C, with PLL distribution or external OSC crystal oscillator as the clock source.

The LPI2C function clock is asynchronous to the bus clock and can still be enabled in low-power mode. At this time, the I2C bus of the LPI2C host can still transmit data.

LPI2C slaves also use functional clocks to support digital filter and data hold time configuration.

The LPI2C master separates the functional clock through a prescaler, and the resulting frequency must be at least 8 times faster than the I2C bus bandwidth.

②External clock.

The LPI2C slave logic gets clocked directly from external pins SCL and SDA (or SCLS and SDAS if master and slave are implemented on different pins).

This allows the LPI2C slave to remain active even if the LPI2C function clock is disabled.

Note: If the LPI2C function clock is disabled, the LPI2C slave digital filter must be disabled, which may affect compliance with certain timing parameters in the I2C specification, such as data hold time.

③Bus clock.

Refers to the clock of the RT1052 internal peripheral bus (Internal Soc Peripheral Bus).

The bus clock is used only for bus access control and configuration registers.

The bus clock frequency must be sufficient to support the data bandwidth requirements of the LPI2C master and slave registers.

The comparison of 2-wire I2C and 4-wire I2C pin functions is as follows.

It can be seen that 4-wire I2C has additional SCLS and SDAS clock lines and data lines.

When LPI2C is configured in master and slave independent pin mode, the SCL and SDA lines are used in master mode, while the SCLS and SDAS lines are used in slave mode without interfering with each other.

HREQ also adds a pin, which is used by external devices to request communication from the LPI2C host.

in conclusion:

4-wire mode: SCL and SDA correspond to input, SCLS and SDAS correspond to output.

The master and slave machines are independent: SCLS , SDAS corresponds to the slave machine.

The 2-wire bus structure diagram is shown below.

It can be seen that the 2-wire bus diagram in the manual is the same as what we usually see.

The 4-wire bus structure diagram is shown below.

The dotted line is the hardware driver circuit in the figure below.

In 4-wire mode, the hardware will limit whether the data line is SDA (input) or SDAS (output). When the sending and receiving are different, the so-called 4-wire is actually fake, but the data is carried separately. The advantage of this is that there is less interference.

Some applications may provide a large amount of loading and noise on the I2C bus. To ensure reliable I2C operation, a 4-wire interface can be used, dividing the 2 lines into input and output.

Using the transistors, resistors, and diodes shown above, you can build your own inexpensive line driver.

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