[Practical Sharing] | A brief discussion on the impact of power rail noise on clock jitter (I)
In digital circuits, a binary signal stream is represented by a voltage (or current) waveform. However, signals in nature are actually analog, not digital, and all signals are affected by noise, distortion, and loss. The main issues considered in signal integrity are ringing, crosstalk, ground bounce, skew, signal loss, and noise in the power supply. --Excerpt from Wikipedia (Signal Integrity).
Accurate periodic sampling clock is the prerequisite for ensuring correct communication in digital systems. If the clock signal is offset, it will cause changes in the transmitted digital signal flow, such as delay, bit error, etc. In high-speed digital systems, as the clock rate enters the GHz level, the primary goal is to ensure that the signal is transmitted from the source to the receiving end intact and without distortion. Often, poor power integrity will affect the clock signal, which will cause signal integrity problems.
The design of high-speed digital products not only includes signal integrity issues, but also power integrity issues. The evaluation of power rail noise in digital systems will directly reflect the quality of power integrity. This article will introduce how power rail noise in digital products affects clock jitter in the system.
The DC voltage in digital circuits, or the power rail waveform, often looks like it is pure and straight. However, when we zoom in with an oscilloscope, we find that it is not.
There are AC fluctuation components on the power rail.
In addition to the fluctuations introduced by the switching power supply, the power rail is also affected by coupled noise. When ringing occurs on the PDN, it will cause the clock signal output by the chip to deviate. The deviation on the rising edge of the clock signal is what we commonly call jitter.
The chips in digital systems are usually composed of CMOS integrated circuits, whose switching thresholds fluctuate due to the noise of the power rail, thereby causing jitter in the system output clock or data.
As can be seen from the figure below, the magnitude of the power rail noise fluctuation will affect the jitter size. The smaller the power rail fluctuation, the smaller the jitter of the clock signal will be.
The ratio of power rail noise to the slope of the clock signal determines the magnitude of the jitter. The relationship between power rail noise and jitter can be described by the following formula:
If you want to verify the impact of jitter, you need to accurately measure the power rail noise. However, it is challenging to accurately evaluate the power integrity in today's electronic products. Take the most common digital electronic product, mobile phones, as an example. With the evolution of mobile phones, the size is getting smaller and smaller, while the internal IC integration is getting higher and higher, the current density is getting higher and higher, and the power consumption is decreasing, which requires the input voltage to be reduced (from the typical 5V, 3V to 1V), and even the voltage tolerance is also reduced (10% to 5%, or even 1%). This will cause challenges to the power rail measurement.
The R&S RT-ZPR power rail probe is the best choice for this challenge. It not only has extremely low system noise (attenuation ratio 1:1), but also has a high bandwidth range of 2 GHz/4 GHz, which can measure power rail noise in a higher frequency range.
Take actual measurement as an example: compare the DC voltage Vpp tested using the RT-ZPR power rail probe and the traditional RT-ZP1X ripple probe:
The 38 MHz bandwidth 1:1 passive probe RT-ZP1X will miss high-frequency components and fail to show the existence of spikes, thus underestimating the Vpp measurement value. However, the power rail probe RT-ZPR20 with the same attenuation ratio and a bandwidth of up to 2 GHz can capture and measure high-frequency transients and has extremely low noise. It is not difficult to see that a high-bandwidth power rail probe is required to measure the correct Vpp value for high-frequency transients.
In summary, the power rail signal is not completely straight, it will be affected by noise, which will affect the stability of the system clock. The power rail voltage in today's digital products is getting lower and lower, and the required tolerance is becoming more and more stringent, which poses a challenge to measuring the power rail signal. Rohde & Schwarz's power rail probe RT-ZPR fully meets these challenges and can perform accurate measurements (high bandwidth, high sensitivity, low noise and large offset compensation). In the next issue, we will continue to use a measurement case to illustrate the impact of power rail noise on the jitter of digital products.
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