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As the adoption of RS-485 fieldbuses steadily grows, and Industry 4.0 accelerates the development of smart, connected factories, we need to ensure that fieldbus technology is continuously optimized to support smart systems. Optimized fieldbus technology must carefully balance the two factors of EMC stability and data transmission reliability.
Unreliable data transmission can degrade overall system performance. In motion control applications, fieldbuses are typically used to implement closed-loop position control of single-axis or multi-axis motors. These motors are typically in a high data rate, long cable transmission line state, as shown in Figure 1. If the position control is unreliable, the actual performance will be reduced, the defect rate will increase, and the factory productivity will be reduced. In wireless infrastructure applications, fieldbuses are typically used to implement tilt/position control of antennas, so accurate data transmission is critical. Different levels of EMC protection are required in motion control and wireless infrastructure applications, as shown in Figure 1. Motion control applications are often in an electrically noisy environment, which can cause data errors. For wireless infrastructure, it must be protected from indirect lightning damage in an exposed environment.
Figure 1. EMC, data rate, and cable length requirements for RS-485.
For these demanding applications, the cable timing performance of RS-485 transceivers needs to be carefully examined to ensure system reliability and EMC characteristics. This article will introduce several important system timing and communication cable concepts; explain some key performance indicators, including clock and data distribution, cable drive capability; and show the advantages of using the next-generation ADM3065E/ADM3066E RS-485 transceivers for industrial applications.
To achieve reliable data transmission over long cables at high data rates, it is important to consider some important factors affecting RS-485, such as timing performance concepts such as jitter and skew that are typically associated with low-voltage differential signaling (LVDS). Both jitter and skew caused by RS-485 transceivers and system cables need to be considered.
Jitter can be quantified as the time interval error; that is, the difference between the expected arrival time of a signal transition and the actual arrival time. There are many factors that contribute to jitter in a communication link. Basically, each factor that contributes to jitter can be described as either random or deterministic. Random jitter can be described by a Gaussian distribution and generally originates from thermal noise and broadband scatter noise within the semiconductor. Deterministic jitter comes from within the communication system; for example, duty cycle distortion, crosstalk, periodic external noise sources, or intersymbol interference. For communication systems using the RS-485 standard, deterministic jitter is more noticeable at data rates below 100 MHz.
Peak-to-peak jitter is a useful measure of the overall performance of a system's jitter from deterministic sources. It can be measured in the time domain by overlaying a large number of signal transitions on the same display (commonly known as an eye diagram). This can be done using an infinite-duration oscilloscope display or using the oscilloscope's built-in jitter decomposition software, as shown in Figure 2.
Figure 2. Time interval error, jitter, and eye diagram.
The width of the overlapping transitions is the peak-to-peak jitter, and the empty space in between is called the eye. This eye is the area that can be sampled by the receiving node at the far end of a long RS-485 cable. The larger the eye width, the wider the window that the receiving node can sample, and the lower the risk of receiving an erroneous bit. The usable eye is primarily affected by deterministic jitter from the RS-485 driver and receiver, as well as the interconnecting cable.
Figure 3 shows the various sources of jitter in a communications network. In RS-485 based communications systems, the two major factors that affect timing performance are transceiver pulse skew and intersymbol interference. Pulse skew, also known as pulse width distortion or duty cycle distortion, is a type of deterministic jitter generated by the transceiver at the transmit and receive nodes. Pulse skew is defined as the difference in propagation delay between the rising and falling edges of a signal. In differential communications, this skew creates asymmetric crossover points and mismatched durations of transmitted 0s and 1s. In clock distribution systems, excessive pulse skew manifests itself as duty cycle distortion of the transmitted clock. In data distribution systems, this asymmetry increases the peak-to-peak jitter shown in the eye diagram. In both cases, excessive pulse skew can adversely affect the signal transmitted over RS-485 and degrade the available sampling window and overall system performance.
Figure 3. Major contributors to jitter in RS-485 communications networks.
Intersymbol interference (ISI) occurs when the arrival time of a signal edge is affected by the data pattern that processes that edge. The effects of ISI become more pronounced in applications with long cable interconnects, making it a critical factor affecting RS-485 networks. Longer interconnects create an RC time constant where the cable capacitance is not fully charged at the end of a single bit period. In applications where the transmitted data consists only of the clock, this type of ISI does not exist. ISI can also be caused by impedance mismatches on the cable transmission lines (due to the use of short stubs or improper termination resistors). RS-485 transceivers with high output drive capabilities can generally help minimize the effects of ISI because they take less time to charge the RS-485 cable load capacitance.
The percentage of peak-to-peak jitter tolerance is highly application specific, with 10% jitter being used as a benchmark for RS-485 transceiver and cable performance. Excessive jitter and skew can affect the sampling performance of the RS-485 transceiver at the receiving end, increasing the risk of communication errors. In a properly terminated transmission network, choosing an optimized transceiver to minimize transceiver pulse skew and intersymbol interference effects will result in a more reliable, error-free communication link.
The TIA-485-A/EIA-485-A RS-485 standard provides specifications for the design and operating range of RS-485 transmitters and receivers, including voltage output differential (VOD), short-circuit characteristics, common-mode loading, and input supply thresholds and ranges. The TIA-485-A/EIA-485-A standard does not specify the timing performance of RS-485, including skew and jitter, and is optimized by IC vendors based on product data sheet specifications.
Other standards, such as the TIA-568-B.2/EIA-568-B.2 twisted-pair telecommunications standard, provide background on the effects of cable ac and dc on RS-485 signal quality. This standard provides considerations and test procedures for jitter, skew, and other timing measurements, and sets performance limits; for example, the maximum skew allowed for 5e cable is 45 ns/100 m. ADI Application Note AN-1399 discusses the TIA-568-B.2/EIA-568-B.2 standard in detail, as well as the effects of using non-ideal cables on system performance.
While the available standards and product data sheets provide a lot of useful information, any meaningful characterization of system timing performance requires measuring the performance of RS-485 transceivers over long cables.
The ADM3065E RS-485 transceiver has ultra-low transmitter and receiver skew performance, making it ideal for transmitting precision clocks, typically using motor encoding standards. The ADM3065E has been shown to have less than 5% deterministic jitter over typical cable lengths in motor control applications (Figures 4 and 5). The wide supply voltage range of the ADM3065E allows this level of timing performance to be used in applications that require a 3.3 V or 5 V transceiver supply.
Figure 4. Typical clock jitter performance of the ADM3065E.
Figure 5. ADM3065E receive eye diagram: 25 MHz clock distributed over 100 m of cable.
In addition to excellent clock distribution, the ADM3065E timing performance also supports reliable data distribution, as well as high-speed outputs and minimal additive jitter. Figure 6 shows that by using the ADM3065E, the timing constraints of RS-485 data communications are greatly relaxed. The jitter of standard RS-485 transceivers is typically 10% or less. The ADM3065E can operate at speeds of more than 20 Mbps over cables up to 100 meters long and still maintain 10% jitter at the receiving node. This low level of jitter reduces the risk of erroneous sampling at the receiving data node, achieving transmission reliability that cannot be achieved using typical RS-485 transceivers. For applications where the receiving node can tolerate up to 20% jitter, data rates up to 35 Mbps can be achieved within 100 meters of cable.
Figure 6. The ADM3065E receive data node has excellent jitter performance.
This timing performance makes the ADM3065E an ideal choice for motor control encoder communication interfaces. For each data packet transmitted using the EnDat 2.2 encoder protocol, data transmission is synchronized to the falling edge of the clock. Figure 7 shows that after the initial calculation of the absolute position (T CAL ), the start bit begins the transmission of data from the encoder back to the host controller. The subsequent error bits (F1, F2) indicate the specific position when the encoder caused a fault error. The encoder then sends an absolute position value, starting with LS, followed by the data. The integrity of the clock and data signals is critical to successfully sending positioning and error signals over long cables, and EnDat 2.2 specifies a maximum jitter of 10%. This is the maximum jitter requirement specified by EnDat 2.2 for a 20-meter cable and a 16 MHz clock rate. Figure 4 shows that the ADM3065E can meet this requirement with a clock jitter of only 5%, and Figure 6 shows that the ADM3065E can meet the data transmission jitter requirements, but standard RS-485 transceivers cannot.
Figure 7. EnDat 2.2 physical layer and protocol for clock/data synchronization (adapted from the EnDat 2.2 diagram).
Analog Devices has characterized the excellent cable timing performance of the ADM3065E transceiver, ensuring that system designers have the necessary information to successfully develop designs that meet the EnDat 2.2 specification.
The TIA-485-A/EIA-485-A RS-485 standard requires a compliant RS-485 driver to produce a differential voltage amplitude, VOD, of at least 1.5 V in a fully loaded network. This 1.5 VOD allows for a 1.3 V dc voltage attenuation in long cables, while the RS-485 receiver is required to operate with a minimum 200 mV input differential voltage. The ADM3065E is designed to output a minimum VOD of 2.1 V when supplied with 5 V, which exceeds the RS-485 specification.
A fully loaded RS-485 network is equivalent to a 54 Ω differential load, which simulates a doubly terminated bus consisting of two 120 Ω resistors, and the other 750 Ω is formed by 32 1 unit load (or 12 kΩ) connections. The ADM3065E uses a proprietary output architecture that maximizes VOD while meeting the common-mode voltage range requirements and exceeds the requirements of TIA-485-A/EIA-485-A. Figure 8 shows that the ADM3065E produces a drive force that exceeds the RS-485 standard requirement by >210% when powered from a 3.3 V rail and >300% when powered from a 5 V rail. This extends the communication range of the ADM3065E family, supporting more remote nodes and higher noise margins than conventional RS-485 transceivers.
Figure 8. The ADM3065E exceeds RS-485 driver requirements over a wide supply range.
Figure 9 further illustrates this point with typical application performance over 1000 m of cable. The ADM3065E performs 30% better than a standard RS-485 transceiver when communicating over standard AWG 24 cable—a 30% better noise margin at the receiving node, or a 30% increase in maximum cable length at low data rates. This performance is ideal for wireless infrastructure applications where RS-485 cables can be hundreds of meters long.
Figure 9. The ADM3065E provides excellent differential signaling for ultra-long reach applications.
RS-485 signals are transmitted in a balanced differential manner, which inherently has a certain degree of anti-interference capability. System noise is equally coupled to each wire in the RS-485 twisted-pair cable. The twisted pair allows the generated noise current to flow in opposite directions, canceling out the electromagnetic fields coupled to the RS-485 bus. This reduces the electromagnetic susceptibility of the system. In addition, the enhanced 2.1 V drive strength of the ADM3065E supports a higher signal-to-noise ratio (SNR) in communications. In long cable transmissions, such as the distance between the ground and wireless base station antennas of up to several hundred meters, enhanced SNR performance and excellent signal integrity can ensure accurate and reliable tilt/position control of the antenna.
Figure 10. Wireless infrastructure cable lengths can exceed several hundred meters.
As shown in Figure 1, EMC protection is required for RS-485 transceivers, which are directly connected to the outside world through adjacent connectors and cables. For example, ESD on exposed RS-485 connectors and cables from encoders to motor drives is a common system hazard. The system-level IEC 61800-3 standard, which is related to EMC immunity requirements for variable speed electric drive systems, requires a minimum of ±4 kV (contact)/±8 kV (air) IEC 61000-4-2 ESD protection. The ADM3065E exceeds this requirement, providing ±12 kV (contact)/±12 kV (air) IEC 61000-4-2 ESD protection.
For wireless infrastructure applications, enhanced EMC protection is required to prevent damage from lightning strikes. Adding an SM712 TVS and two 10 Ω coordination resistors to the ADM3065E input can enhance EMC protection to provide up to ±30 kV 61000-4-2 ESD protection and ±1 kV IEC 61000-4-5 surge protection.
To improve noise immunity in electrically demanding applications such as motor control, process automation, and wireless infrastructure, electrical isolation can be added. Using ADI ’s iCoupler® and isoPower® technologies , galvanic isolation with reinforced insulation and 5 kV rms transient voltage can be added to the ADM3065E. The ADuM231D provides three channels of 5 kV rms signal isolation with precision timing performance, which can operate reliably at speeds up to 25 Mbps. The ADuM6028 isolated dc-to-dc converter provides the required isolated power with a withstand rating of 5 kV rms. EMC-related standards such as EN 55022 Class B/CISPR 22 can be easily met using two ferrite beads, resulting in a compact 6 mm × 7.5 mm isolated dc-to-dc solution.
Figure 11. Complete 25 Mbps signal and power isolated RS-485 solution with ESD, EFT, and surge protection.
ADI's ADM3065E RS-485 transceiver outperforms industry standards, enabling faster, longer-distance communications than standard RS-485 devices. At the 10% jitter level specified in EnDat 2.2, the ADM3065E allows users to operate at a 16 MHz clock rate with up to 20 meters of cable, which is difficult for standard RS-485 devices to meet. The ADM3065E's drive force exceeds the RS-485 bus drive requirements by 300%, providing better reliability and higher noise tolerance when using longer cables. Immunity can be improved by adding iCoupler isolation, including the ADuM231D signal isolator, and the industry's smallest isolated power solution, the ADuM6028.