How to choose a clock generator? These three aspects must be carefully considered!

Figure 1. Clock timing solution for a typical LTE base station using MIMO architecture

The clock source used to achieve synchronization between base stations is generally derived from a GPS (Global Positioning System) or CPRI (Common Public Radio Interface) link. This source generally has excellent long-term frequency stability; however, it requires frequency conversion to the required local reference frequency to achieve good short-term stability or jitter. A high-performance clock generator performs the frequency conversion operation and provides low-jitter clock signals, which may be distributed to various base station components. Selecting the best clock generator is critical because a suboptimal reference clock will increase the LO phase noise, which will result in increased transmit/receive EVM (error vector magnitude) and system SNR (signal-to-noise ratio). High clock jitter and noise floor also affect data converters because it will reduce the system SNR and cause data converter spurious emissions, further reducing the data converter's SFDR (spurious-free dynamic range). As a result, a low-performance clock source will ultimately reduce system capacity and throughput.

Although there are many definitions of clock jitter, the most appropriate definition in data converter applications is phase jitter, which is expressed in ps rms or fs rms in the time domain. Phase jitter (PJBW) is the jitter derived by integrating the phase noise of the clock signal over a specific offset range from the carrier and is calculated as follows:

fCLK is the operating frequency; fMIN _{/ fMAX} is _the bandwidth of interest, and S(fCLK ₎ is the SSB phase noise. The upper and lower limits of the integration bandwidth (fMIN _/ fMAX ₎ vary from application to application, depending on the relevant spectral components to which the design is sensitive. The designer's goal is to select a clock generator with the lowest integrated noise or lowest phase jitter in the required bandwidth. Traditionally, clock generators have been characterized over an integration range of 12 kHz to 20 MHz, which is also specified for optical communication interfaces such as SONET. While this may be suitable for some data converter applications, a wider integration spectrum, specifically above 20 MHz, is usually required to capture the relevant noise profile of a high-speed data converter sampling clock. When measuring phase noise, the noise is far away from the carrier frequency.

For example, the actual clock frequency used for sampling in a data converter is often referred to as being far from the carrier phase noise. The limit of this noise is often referred to as the phase noise floor, as shown in Figure 2. This figure shows an actual measurement of an ADI HMC1032LP6GE clock generator. The phase noise floor is particularly important in data converter applications because the converter SNR is extremely sensitive to broadband noise at its clock input. When designers are evaluating clock generator options, phase noise floor performance must be considered as a key benchmark.

Figure 2. Phase noise and jitter performance of the HMC1032LP6GE.

In Figure 2, the integrated phase jitter is ~112 fs rms at an operating frequency of ~160 MHz, the integrated bandwidth is 12 kHz to 20 MHz, and the phase noise floor is ~–168 dBc/Hz. Here It is worth noting that when selecting the most appropriate clock generator for a data converter, designers should refer not only to frequency-domain phase noise measurements, but also to time-domain clock signal quality measurements such as duty cycle and rise/fall times.

To describe the effect of clock noise on data converter performance, it helps to think of the converter as a digital mixer, with one minor difference. In a mixer, the phase noise of the LO is added to the signal being mixed. In a data converter, the phase noise of the clock is added to the converted output, but is suppressed by the ratio of the signal to the clock frequency. Clock jitter causes sampling time errors, which manifests as a degradation in SNR. ( Time jitter (Tjitter) is the rms error in the sampling time in seconds)

In some applications, clock filters may be used to reduce the jitter of the clock signal, but this approach has significant drawbacks:

A more practical approach is to maximize the slope of the clock signal using a low-noise clock driver with a fast slew rate and high output drive capability. This approach optimizes performance for the following reasons:

A very low clock noise floor is critical. Clock jitter noise that is far from the carrier is sampled in the ADC and added to the ADC digital output frequency band. This frequency band is limited by the Nyquist frequency, which is defined as:

Clock jitter is typically dominated by the broadband white noise floor of the ADC clock signal. While the SNR performance of an ADC depends on many factors, the impact of broadband jitter on the clock signal is determined by the following equation:

As shown in the above equation, unlike a mixer, the SNR contribution of clock jitter is proportional to the ADC analog input frequency (f _IN ).

When driving an ADC, clock noise is limited by the bandwidth in the clock driver path, which is typically dominated by the ADC clock input capacitance. Wideband clock noise modulates the larger input signal and adds to the ADC output spectrum. Phase noise in the clock path degrades the output SNR performance in proportion to the input signal amplitude and frequency. The worst case is when a large high frequency signal is present in the presence of a small signal.

In modern radio communication systems, it is often the case that multiple carrier signals are present at the input, and then each target signal is filtered in the DSP to match the signal bandwidth. In many cases, a large unwanted signal at one frequency will mix with the clock noise, resulting in a reduction in the available SNR at other frequencies in the ADC passband. In this case, the target SNR is the SNR in the desired signal bandwidth. In addition, the SNR _JITTER value above is actually relative to the amplitude of the largest signal (usually an unwanted signal or blocking signal).

The output noise in the desired signal band of interest is determined by:

The result of step b is simply to modify the SNR equation shown previously as follows:

Finally, the maximum available SNR in the signal band of interest in the presence of a full-scale blocking signal is simply the sum of the jitter and dc-contributed noise powers.

For example, a 500 MSPS data converter with an ENOB of 12.5 bits at dc, or an SNR of 75 dB, is evaluated at 250 MHz in a bandwidth equal to half the sampling rate. If the bandwidth of the signal of interest is 5 MHz, the possible SNR near dc (5 MHz bandwidth, perfect clock) is 75 + 10 × log ₁₀ (250/5) = 92 dB.

However, the ADC clock is not perfect; Figure 3 shows the performance degradation effect in the 5 MHz wanted signal bandwidth as a function of the large unwanted signal input on the x-axis frequency. As jitter increases, the effect of the unwanted signal becomes more severe, and the same is true as the input frequency increases. If the amplitude of the unwanted signal decreases, the usable SNR will increase proportionally.

Figure 3. ADC SNR vs. clock jitter and input frequency.

For example, if a full-scale 5 MHz unwanted W-CDMA signal is sampled at a 200 MHz input using a high-quality 500 MHz clock (such as the HMC1034LP6GE) with 70 fs jitter when running in integer mode, the SNR in the nearby 5 MHz channel will be approximately 91 dB. Conversely, if the clock jitter is reduced to 500 fs, the same data converter and signal will only exhibit an SNR of 81 dB, a 10 dB degradation in performance.

Inputting the same signal into the data converter at 400 MHz with a 70 fs clock will produce an SNR of 88 dB. Similarly, with a 500 fs clock, the SNR value drops to only 75 dB.