What is the JESD204 standard and why should we pay attention to it?

In April 2006, the initial version of JESD204 was released. This version describes a multi-Gb serial data link between a converter and a receiver (usually an FPGA or ASIC). In the initial version of JESD204, the serial data link was defined as a single serial lane between one or more converters and a receiver. Figure 1 provides a graphical illustration. The lanes in the figure represent the physical interface between the M converters and receivers, which consists of differential pairs using current mode logic (CML) drivers and receivers. The link shown is the serial data link between the converter and the receiver. The frame clock is routed to both the converter and the receiver and provides the clock for the JESD204 link between the devices .

The lane data rates are defined between 312.5 Mbps and 3.125 Gbps, with source and load impedances defined as 100 Ω ±20%. The differential level is defined as nominally 800 mV peak-to-peak, with common-mode levels ranging from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding, with an embedded clock, which eliminates the need to route additional clock lines and the associated complexity of aligning the data being transmitted at the higher data rates with the additional clock signal. As the JESD204 standard began to gain popularity, it became recognized that the standard needed to be revised to support multiple, aligned serial lanes with multiple converters to accommodate the increasing speeds and resolutions of converters.

This realization led to the release of the first revision of JESD204, JESD204A. This revision added the ability to support multiple aligned serial lanes with multiple converters. The supported lane data rates for this revision remain from 312.5 Mbps to 3.125 Gbps, and the frame clock and electrical interface specifications are preserved. The addition of support for multiple aligned serial lanes allows converters with high sample rates and high resolution to reach the maximum supported data rate of 3.125 Gbps. Figure 2 graphically represents the added functionality of the JESD204A revision, which supports multiple lanes.

While both the original JESD204 standard and the revised JESD204A standard offer higher performance than older interface standards, they are still missing a key element. This missing element is deterministic latency of serial data on the link. For converters, knowing the timing relationship between the sampled signal and its digital representation is critical to correctly reconstructing the analog domain sampled signal when it is received (although this is for ADCs, the situation is similar for DACs). This timing relationship is affected by the converter's latency, which for ADCs is defined as the number of clock cycles from the moment the input signal sampling edge occurs until the converter outputs the digital signal. Similarly, for DACs, latency is defined as the number of clock cycles from the moment the digital signal enters the DAC until the analog output begins to transition. The JESD204 and JESD204A standards do not define a function that can deterministically set converter latency and serial digital input/output. In addition, converter speeds and resolutions continue to increase. These factors led to the second version of the standard, JESD204B.

In July 2011, the second version of the standard was released, called JESD204B, which is the current version. One of the important aspects of the revised standard is the inclusion of provisions for achieving deterministic latency. In addition, the supported data rate has been increased to 12.5 Gbps and the devices are divided into different speed grades. This revision of the standard uses the device clock as the primary clock source instead of the frame clock as in the previous version. Figure 3 shows the new features in the JESD204B version.

In the two previous versions of the JESD204 standard, there were no provisions to ensure deterministic latency through the interface. The JESD204B revision corrects this problem by providing a mechanism to ensure that latency is reproducible and deterministic between power-up cycles and during link resynchronization. One mechanism is to use the SYNC~ input signal at a well-defined moment to initiate the initial lane alignment sequence of converters in all lanes simultaneously. Another mechanism is to use the SYSREF signal, a new signal defined by JESD204B. The SYSREF signal serves as the master timing reference to align all internal dividers with the device clock and local multiframe clock at each transmitter and receiver. This helps ensure deterministic latency through the system. The JESD204B specification defines three device subclasses: Subclass 0—no support for deterministic latency ; Subclass 1—deterministic latency using SYSREF ; and Subclass 2—deterministic latency using SYNC~ . Subclass 0 can be easily compared to a JESD204A link. Subclass 1 was originally targeted at converters operating at 500MSPS or above, while Subclass 2 was originally targeted at converters operating below 500MSPS.

In addition to defining latency, JESD204B supports lane data rates up to 12.5 Gbps and divides devices into three different speed grades: Source and load impedances are the same for all three speed grades, defined as 100 Ω ±20%. The first speed grade is the same lane data rate as defined by the JESD204 and JESD204A standards, i.e., the lane data electrical interface is up to 3.125 Gbps. The second speed grade of JESD204B defines an electrical interface with lane data rates up to 6.375 Gbps. This speed grade reduces the minimum differential level for the first speed grade from 500 mV p-p to 400 mV p-p. The third speed grade of JESD204B defines an electrical interface with lane data rates up to 12.5 Gbps. This speed grade reduces the minimum differential level required for the electrical interface to 360 mV p-p. As the lane data rates increase for the different speed grades, the minimum required differential level is reduced by reducing the required driver slew rate to make physical implementation easier.

To provide more flexibility, the JESD204B revision uses a device clock instead of a frame clock. In previous revisions of JESD204 and JESD204A, the frame clock was the absolute time reference for the JESD204 system. The frame clock and converter sample clock were usually the same. This did not allow for sufficient flexibility and added unnecessary complexity to the system design when routing this same signal to multiple devices and accounting for skew between different routing paths. In JESD204B, the device clock is used as the time reference for each element of the JESD204 system. Each converter and receiver is fed a device clock generated by a clock generator circuit that generates all device clocks from the same source. This allows for more flexibility in system design, but requires that the relationship between the frame clock and the device clock be specified for a given device.

JESD204 is expected to evolve in a similar manner over the next few years, just as LVDS began to replace CMOS as the digital interface technology of choice for converters a few years ago. Although CMOS technology is still in use today, it has been largely replaced by LVDS. The speed and resolution of converters, as well as the need for lower power consumption, will eventually make CMOS and LVDS unsuitable for converters. As the data rate of the CMOS output increases, the transient current will also increase, resulting in higher power consumption. Although the current and power consumption of LVDS remain relatively flat, the maximum speed that the interface can support is limited.

This is due to the driver architecture and the numerous data lines that must all be synchronized to a data clock. Figure 4 shows the different power requirements for CMOS, LVDS, and CML outputs of a dual-channel 14-bit ADC.

At about 150 MSP to 200 MSPS and 14-bit resolution, CML output drivers begin to gain in efficiency in terms of power consumption. The advantage of CML is that it requires fewer output pairs for a given resolution than LVDS and CMOS drivers because of the serialization of the data. CML drivers as described by the JESD204B interface specification have an additional advantage because the specification requires reduced peak-to-peak voltage levels as the sampling rate increases and increases the output line rate.

Likewise, for a given converter resolution and sample rate, the number of pins required is greatly reduced. Table 1 shows the pin counts for three different interfaces using 200 MSPS converters with various channel counts and bit resolutions. In both CMOS and LVDS outputs, assuming the clock is synchronous for each lane data, the maximum data rate for JESD204B data transmission is 4.0 Gbps when using CML outputs. From this table, it can be seen that the advantage of JESD204B using CML drivers is significant, with a greatly reduced pin count.

Table 1. Pin Count Comparison—200 MSPS ADCs

ADI, the industry’s leading data converter supplier, foresaw the trend of driving converter digital interfaces toward JESD204 (defined by JEDEC). ADI has been involved in the definition of the standard since the initial release of the JESD204 specification. To date, ADI has released several converters with outputs compatible with JESD204 and JESD204A, and is currently developing products with outputs compatible with JESD204B. The AD9639 is a quad-channel, 12-bit, 170 MSPS/210 MSPS ADC with an integrated JESD204 interface. The AD9644 and AD9641 are 14-bit, 80 MSPS/155 MSPS, dual-channel/single-channel ADCs with an integrated JESD204A interface. On the DAC side, the recently released AD9128 is a dual-channel, 16-bit, 1.25 GSPS DAC with an integrated JESD204A interface.

As converter speeds and resolutions increase, the need for more efficient digital interfaces grows. The industry has recognized this with the invention of the JESD204 serial data interface. The interface specification is still evolving to provide a better and faster way to transfer data between converters and FPGAs (or ASICs). The interface has been improved and implemented through two revisions to accommodate the growing demand for higher speed and resolution converters. Looking at the evolution of converter digital interfaces, it is clear that JESD204 is poised to become the industry standard for digital interfaces to converters. Each revision has addressed the need to improve its implementation and allowed the standard to evolve to accommodate changes in converter technology and the new requirements that result. As system designs become more complex and converter performance requirements increase, the JESD204 standard should be able to be further adapted and evolved to meet the needs of new designs.