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When the half-pitch of NAND flash memory reached 20 nm, non-volatile storage capacity reached 64 Gb. After reaching 14 nm, the half-pitch of NAND flash memory stopped decreasing, and now it has entered the 3D era. However, recently 3D XPoint has found applications in the Optane platform. The lithography technology used to pattern the 20 nm half-pitch lines that make up these memories is another opportunity to look at the basic aspects and limitations of the lithography methods currently known in the industry.
A method for patterning 20 nm half-pitch lines is self-aligned double patterning (SADP). This method starts with 80 nm pitch lines, which are really just supporting sidewall layers called spacers (Figure 1). The spacers are etched vertically leaving only the sidewall portions. The original lines are then removed, and the spacers form a 40 nm pitch line pattern.
Figure 1. When using SADP (self-aligned double patterning), the sidewall spacers define lines that are twice as large as the starting photoresist.
For SADP, feature size is determined by spacer width, which in turn is controlled by deposition. Lithography does not affect feature size, but errors can produce alternating pitch errors ("pitch walk"); this can be compensated by synchronizing lithography with subsequent spacer deposition and etch.
40 nm Line Pitch Lithography Considerations
80 nm pitch lines can be formed by immersion lithography using a scanner with a 1.35 numerical aperture and a 193 nm wavelength. Although this resolution is achievable on this tool, the illumination must be limited. The distance of the light source from the center in the y direction affects the phase difference between the 0th and 1st diffraction orders for the 80 nm pitch, which is also proportional to the defocus distance. Additionally, polarization should be limited for best results.
Figure 2. An 80 nm pitch using immersion lithography requires very limited illumination. Excluding the orange portion of the dipole will improve the defocus window.
EUV tools can also directly achieve 40 nm pitches without using SADP. However, illumination is still limited to the lobe dipole region.
Figure 3. The 40 nm pitch of EUV lithography is directly affected by rotation. The labels indicate the range of phase difference between 0th and 1st order in degrees. The red open circles indicate the rotation of the original target source point (edge relative to center). Some are rotated to the point where they can no longer produce any image. Others are affected by greater defocus.
The main difficulty here is the rotation of the EUV illumination (since EUV projection systems must use off-axis mirrors) from the center of the arc-shaped slit (i.e., the exposure field) to the edge. On the NXE:3400, it is more than 18 degrees. As shown in Figure 3, at a defocus of 30 nm, the rotation can extend the range of phase differences between the 0th and 1st orders from 30 degrees to more than 60 degrees for the selected set of source points. This is expected because the rotation naturally moves a distance in the y direction. Such a large range will cause further image degradation and also divide the photons into more phase difference bins, resulting in worse randomness. Moreover, due to pushing the first order out of the numerical aperture, some points are even rotated to a position where they can no longer produce an image.
The options for 40 nm line spacing are summarized below:
Intersection considerations
3D XPoint has a new component, the selector memory stack with 40 nm x and y pitches. Assuming the 40 nm pitch lines are patterned via SADP, there are three options for patterning the stack. First, the stack can be patterned as a 2D array using a 2D SADP approach. Alternatively, the stack can emerge automatically from two interleaved 1D SADP steps, one for the x lines and one for the y lines, as shown below. This, of course, requires an additional mask. Finally, the stack may not even be patterned separately. However, this option carries the risk of merging the lower portion of the crosspoint stack since the profiles are not straight (Figure 4). This can of course be avoided if the dielectric between the stacks is chosen to be etched along with the stacks rather than left alone.
Figure 4. After etching in the first direction, the dielectric is backfilled and then cut in the other direction. However, for the sloped stack profile, the lower part of the stack is shielded from cutting by the upper part of the dielectric.
Crosspoint stack manufacturing options are summarized below:
Assuming 3D XPoint uses the X-SADP + Y-SADP option, a two-layer structure would require 7 SADP instances: bottom line, bottom crosspoint X, bottom crosspoint Y, middle line, top crosspoint X, top crosspoint Y, top line. Going to four layers, this would increase to 13 (5 sets of lines + 4 SADP pairs for the crosspoints between layers). However, integration with line SADP might only require using SADP 5 times to get four layers.
3D NAND also ended up using SADP due to the 20 nm bitline half pitch. If the bitline half pitch needs to be reduced below 20 nm, self-aligned quadruple patterning (SAQP) may be required.
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