Usage of $test$plusargs

chenbingjy

Usage of $test$plusargs [Copy link]

I bought Teacher Xia Yuwen's "Verilog Digital System Design Tutorial" (4th Edition)

There is an example on page 114. I tried to do this experiment but it didn't work.

The code is:

`timescale 10ns/1ns
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;

// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);

reg a,b,c;
initial begin
a=1'b1;b=1'b0;c=1'b1;
if($test$plusargs("DISPLAY_VAR"))
$display("Dispaly=%b",{a,b,c});
else
$display("No Dispaly");
end



endmodule

The book says that variables are displayed only if the flag DISPLAY_VAR is set at runtime. You can specify the +DISPLAY_VAR option to set the flag at program runtime.

I don't know how to set it up, please help me, thank you!

chenbingjy

Do I need to install the Synopsys VCS software to set this flag? I can't find it online or on Taobao. Can an expert tell me where I can find it? Thanks!