Next-generation EUV lithography machine, new transistor, and Moore's Law's "savior"!

Latest update time：2021-09-06

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Editor's Note

I (Takashi Yunogami) became a semiconductor technician when Japan was sweeping the world with DRAM (I was a technician for 16 years until 2002). Since then, I feel that semiconductors have not received as much attention from the world as they do today. This brings up the old question: "When will Moore's Law end?" and "When will the miniaturization of semiconductors stop?"

In the late 1980s and mid-1990s, due to the serious charging damage caused by processes using plasma such as dry etching, further miniaturization of semiconductors was considered impossible. However, Japanese technicians conducted pioneering research. After that, Japan and the United States conducted thorough research, and as a result, plasma dry etching is still used to this day. Therefore, in this regard, semiconductor miniaturization will not stop.

After that, I remember that the question of “Has semiconductor miniaturization reached its limit?” was raised again when ArF exposure equipment reached its resolution limit in 2006 (Figure 1). At that time, I was a professor of business administration at Doshisha University, and I was commissioned by a semiconductor-related company to conduct research. I asked key people involved in the most advanced micro-scaling at the time, “How many nanometers do you think the micro-scaling limit of semiconductors is?” and conducted a survey.

Figure 1. Principles and history of photolithography

It is quite interesting to revisit this survey result now. Therefore, this article is about "When will semiconductor scaling stop?" and "When will Moore's Law come to an end?"

Micro-survey conducted in 2007

Around 2006, the miniaturization of logic device semiconductors was progressing from 65nm to 45nm. However, the most advanced exposure equipment at the time, ArF (now called ArF dry method), had reached its resolution limit, and EUV (extreme ultraviolet light), a candidate for the next generation of exposure equipment, had a lot of problems, and even R&D equipment did not exist. Therefore, the atmosphere of "Isn't the miniaturization of semiconductors over?" floated in the semiconductor industry.

At the time, I was a business administration professor at Doshisha University and asked myself, “When will semiconductor miniaturization stop?” Inspired by this commissioned research, I traveled around the world from July to September 2007 (a full two months), visited cutting-edge semiconductor manufacturers, manufacturing equipment and material manufacturers, the American consortium SEMATECH, and European imec, and surveyed key people involved in miniaturization.

When we asked the question, we looked at logic devices and memory separately. The questions included, for example, what do you think the half pitch (hp) limit will be in nm? Looking back at that time, the pitch of the finest metal wiring (M1) was roughly proportional to the technology node, so the question above was, "What is the hp limit of M1 in nm?" (Figure 2).

Figure 2. Progress and future forecast of semiconductor scaling

Source: Toshiro Hiramoto (Institute of Industrial Technology, University of Tokyo)

In addition, regarding memory, NAND flash memory continues to be two-dimensionally miniaturized, and its level is more advanced than DRAM, so the question asked was "How many nm do you think the hp of the micro wiring M1 (or gate length) of NAND flash memory is?" Figure 3 shows the results of this survey. A, B..., Z represent the serial numbers of the technicians who answered the author's questions (the survey was conducted in the order of A→B→..., Z in time).

Figure 3. " What is the micro-shrinkage limit?" (hp, nm) in the 2007 survey

The limit of miniaturization is easily broken

Judging from the results, many technicians at that time believed that the limit for logic devices was when the hp was 45nm, and the limit for memory was when the hp was 32nm. This miniaturization limit was simply broken by extending the ArF dry method ArF immersion and SADP (Self-Arigined Double Patterning) and other technologies. Even at that time, many technicians believed that "exposure equipment as complex as immersion cannot be started" and "even if SADP is miniaturized, it will not improve the yield."

It is worth mentioning that when I visited TSMC to conduct the survey, I contacted my friends at TSMC and asked them to gather 5 to 6 executives. I projected the previous listening survey results (A to X) onto a slide in the TSMC conference room in Hsinchu, Taiwan.

All the TSMC personnel gathered together laughed. "What are you talking about? Are hp45nm and hp32nm the limit? We have already developed 22nm?" Two of them answered my question, and their answers were hp16nm and hp10nm.

I think the 7nm M1 that TSMC started mass production in 2018 is around hp18nm, and the most advanced 5nm M1 that will be mass produced in 2020 is around hp16nm. Therefore, TSMC's limit at the time was broken in 2020. As for the remaining hp10nm, I think it is close to its limit at TSMC's 3nm and the future 2nm. If the next 1.5nm~1nm is achieved, this limit will be broken.

EUV Survey

From the survey on “What is the nanometer of the miniaturization limit of hp”, we can see that in 2007, the extremely difficult EUV was being developed. The author asked the relevant personnel from A to Z: “Is it impossible to realize the mass production of EUV?” In response to this question, they gave the results shown in Figure 4.

Figure 4. Results of a 2007 survey: “Is it impossible to mass produce EUV machines?”

Here, Figure 4 is divided into two parts, namely, lithography technicians of semiconductor manufacturers, technicians of lithography-related manufacturing equipment or material manufacturers, and technicians other than lithography. Or it can be divided into integration technicians of semiconductor manufacturers and manufacturing equipment or material related personnel other than lithography.

Therefore, among the 18 lithography-related personnel, more than half of the 10 people answered "yes (that is, EUV mass production is not possible)" (Figure 4-1). On the other hand, 7 of the 10 people related to non-lithography answered "no (that is, EUV mass production is possible)" (Figure 4-2). This comparison is really interesting.

Lithography professionals probably felt that “mass production is impossible” because they were well aware of the difficulties in EUV development. However, professionals other than lithography professionals did not trust lithography experts from the beginning, believing that “lithography experts always say it can’t be done and cause a big fuss.”

And from the results, TSMC used EUV lithography machines in large quantities at 7nm+ in 2019, and the wiring also applied EUV to 5nm in 2020. Therefore, it is proved that what the lithography experts said is incorrect. In other words, it is better not to believe that the lithography experts "can't do it".

Thus, in the history of the semiconductor industry, the limits of miniaturization have always been broken, and although the pace has slowed down, it has not stopped. So, what are the prospects for the future?

As for miniaturization, we can see it from the International Technology Roadmap for Semiconductors (ITRS) in 2001. If we continue to follow this roadmap, the company at the forefront is Intel of the United States, which mass-produces processors for PCs, so this roadmap is also called the "Intel Technology Roadmap for Semiconductor".

However, after Intel's 10nm failed in 2016, ITRS also ended that year and was later succeeded by the International Roadmap for Devices and Systems (IRDS), but no one says it is "Intel's roadmap" anymore. In addition, TSMC has replaced Intel and jumped to the forefront of miniaturization. The semiconductor roadmap published by the European consortium imec seems to be closer to reality than IRDS.

Evolution and miniaturization of logic devices CMOS

Figure 5 shows the actual results and forecasts of CMOS evolution and refinement from 1990 to 2030. This chart gives you a glimpse of the past, present, and future of refinement. It is a very moving picture for me.

Figure 5. Technological evolution of logic device CMOS

It was not until the mid-2000s that the scaling of the scaling rules advocated by Robert H.Dennard of IBM progressed smoothly. In other words, a 70% scaling was achieved within 2 years, which increased the operating speed of transistors, reduced power consumption and integration. However, starting around 2003, the scaling speed of gate length slowed down. From this time on, the operating speed of transistors could not be increased even if they were scaled down. Therefore, as auxiliary technologies, the industry began to introduce Cu/Low-k wiring, strained silicon (Strain Si), High-k/Metal gates, FinFETs, etc.

In addition, the calibration of the finest wiring (M1) with "Dense Metal Pichi" written on it in FIG. 5 may be continued while decelerating.

After the failure of Intel's 10nm process in 2016, the main player in scaling has shifted to TSMC. In this diagram, we try to write the technology nodes that TSMC is expected to mass produce after 2018 and in the future.

Comparing the roadmap of imec and the mass production schedule of TSMC, we can see that although the application period of EUV is the same, the period of using Nanosheets with Gate All Around (GAA) structure in CMOS is different. imec envisions 3nm, but TSMC, which is currently investing in risk trial production of this node, still uses FinFET process. They plan to adopt Nanosheets from 2nm.

In any case, the scaling of gate length and micro-wiring M1 will not stop until 2030. According to this graph, it will not even slow down in the next 10 years. On the contrary, if a new CMOS structure called 2D channels is adopted at 1nm, the scaling of gate length will be much better.

The miniaturization of transistors and fine wiring

Figure 6 shows the changes in transistor structure as logic devices shrink.

As shown in the figure, from 3nm to 2nm, transistors change from FinFET to Nanosheets. In addition, imec believes that Forksheets, which separate nMOS and pMOS, are promising from 2nm to 1.5nm. In contrast, in TSMC's mass production plan, Nanosheets appear to be used at 2nm, but there is no mention of Forksheets.

Figure 6. Roadmap for logic device scaling (transistors)

In addition, imec envisions forming a Computational FET (CFET) of nMOS and pMOS vertically around 1.5nm, but there is no trace of this in TSMC's R&D roadmap. However, TSMC is also conducting similar R&D for 2D atomic channels expected to appear at 1nm and beyond.

Transistors have a variety of options like this, and it feels like they are really evolving. However, the development of fine wiring is quite serious. In the Cu wiring that has become the mainstream at present, when the wiring width is refined, scattering due to the grayscale of Cu and the increase in resistance due to scattering of the barrier metal become big problems (Figure 7).

Figure 7. Roadmap for micro-wiring scaling

The current Cu Dual Damascene can only be used up to 3nm. From 2nm, Ru is used for VIA's Hybrid. At 1.5nm, Ru and other materials are directly processed (subtractive), and then it is necessary to make the interlayer insulation film into an air gap. In addition, 1nm and above require the exploration of completely new materials.

In summary, there are various candidates for transistor structures by 2030, but as wiring becomes more sophisticated, the problem of increased resistance is inevitable. If mass production is to be carried out, bold research and development such as material changes must be carried out.

EUV Scaling Roadmap

As mentioned above, between now and 2030, transistors will continue to be miniaturized while their structures change, and fine wiring will continue to be miniaturized while changing its formation methods and materials. How will EUV, which is necessary for this, change?

Figure 8 shows the EUV shrinking roadmap. In the current cutting-edge shrinking, EUV with lens aperture NA = 0.33 (hereinafter referred to as ReglarNA) is used. After that, in order to achieve more refinement, EUV shrinking is implemented in the next four stages of the roadmap (the numbers are slightly different from those in Figure 8).

Figure 8. EUV lithography scaling roadmap

Micro-fabrication with a pitch of 1.28 to 32 nm is the limit of ReglarNA EUV single exposure.

2. SADP under EUV at ReglarNA at 22-24nm pitch

3. After 18nm pitch, EUV with NA=0.55 (called HighNA) is used

4. For further fine processing, use High NA+SADP

The EUV miniaturization roadmap until 2030 is shown above. The problem is that the EUV cost of ReglarNA is 16-18 billion yen, while the EUV cost of High NA, which will be launched around 2024, is 48 billion yen. In the end, is it possible to make a business out of logic semiconductors using such expensive exposure equipment? The wafer cost when using HighNA EUV is another issue to consider.

It is said that HighNA EUV will be available around 2024. TSMC's technology node is about 2nm. This assumption is the same as imec's. Let's calculate the cost of the chip under the premise of applying High NA EUV lithography to the 2nm+ generation (Figure 9).

Figure 9. Wafer cost using HighNA EUV

In this calculation, it is assumed that (1) the price of HighNA's EUV equipment is 1.5 times that of ReglarNA's EUV, and (2) the throughput remains unchanged. Therefore, if ReglarNA's EUV value is 18 billion yen, HighNA's EUV value must be 27 billion yen (if the rumored value is 48 billion yen, the following calculation is invalid).

Under this assumption, the chip manufacturing process consists of three steps: the Front End of Line (FEOL) that forms transistors, the Middle of Line (MOL) that connects transistors and wiring channels, and the Back End of Line (BEOL) that forms multi-layer wiring.

In the 2nm+ technology node, whether to use High NA EUV and how much to use if used, we compare chip costs in three cases.

1. The chip cost when Regular NA EUV is applied to 14 layers and ArF immersion is applied to 2 layers is set to "1". There may be many Regular NA EUF+SADP processes.

2. As an initial solution, if High NA EUV is 4 layers, Regular NA EUV is 6 layers, and ArF immersion is 2 layers, the chip cost can be reduced by 5%.

3. If all are replaced with High NA EUV, the cost can be reduced by 14%.

That means that even if a very expensive High NA EUV lithography machine is used, chip costs can be reduced (but two assumptions must be met). And as can be seen from Figure 9, the cost of FEOL remains almost unchanged, but the processing costs of MOL and BEOL can be greatly reduced. Therefore, if the High NA EUV value is less than 30 billion yen per unit, not only can miniaturization be achieved, but chip costs can also be reduced, so ASML can only work harder.

The era of the Three Powers begins

From now on, the R&D investment of wafer fabs will become more and more difficult and expensive every year, but there is no sign of stopping the miniaturization. Now, TSMC is leading the miniaturization, but Intel, under the leadership of Mr. Pat Gelsinger, is expected to catch up around 2nm. However, Intel recently changed the name of its technology node and officially named it "Intel 20A"

Figure 10. Intel technology node names

In this case, the competition for miniaturization among the three parties, including Samsung and Intel, may intensify in the future, with TSMC, which is at the top, as the center. Even so, why does TSMC, a foundry, continue to miniaturize so crazily?

As I said in my previous article, 10 years ago, miniaturization felt like speeding on a European highway at 200 kilometers per hour. After that, the slowdown of miniaturization was a fact, but even so, TSMC was still speeding on a field path at a speed of 100 kilometers per hour. The width of the field path was getting narrower every year. If you drove the car wrong, you would fall into the field, which was very dangerous. However, they continued to run at a speed of 100 kilometers per hour.

Why does TSMC, as a manufacturer, have to run at a speed of 100 kilometers per hour on the farm road? In fact, I think TSMC, a manufacturer, has no roadmap (it can be said that it is meaningless). TSMC has always been an outsourced manufacturer, so it can only produce and manufacture according to the requirements of the client.

So who could make TSMC "run at 100 km/h on the field path"? That was Apple. After Apple asked for "seemingly impossible miniaturization", TSMC desperately responded.

Is Apple the biggest promoter of the chip industry?

Figure 11 shows the number of smartphones shipped by each company in each quarter. After 2012, Samsung was probably the top shipper. In addition, around 2012, China's Huawei began to grow dramatically, surpassing Samsung in the second quarter of 2020 (Q2) and becoming the world's number one. However, due to US sanctions, Huawei quickly lost momentum after September 15, 2020, as it could not purchase semiconductors from TSMC and other places.

Figure 11. Number of smartphones shipped by company per quarter (until Q2 2021)

Apple's most characteristic shipping habit is to reach the top in the fourth quarter (Q4) of each year. In particular, in Q4 of 2020, the shipment volume reached an all-time high of 90 million units. This is the power of the American Christmas shopping war.

Apple releases a new iPhone around July every year, and aims to mass-produce a total of about 100 million units during the Christmas shopping season in December (actually assembled by Taiwan's Foxconn, which has a large factory cluster in China). Figure 12 shows the statistics of Apple's new iPhones from 2019 to 2023 and the application processor (AP) nodes installed on them, as well as whether their chips use EUV at this technology node.

Figure 12. iPhone AP, Technology Node, and EUV application

In order to catch up with this plan, TSMC must improve the process of N5P, an improved version of 5nm (N5), by 2021 at the latest and manufacture 100 million iPhone APs in Q3. At the same time, in order to mass-produce N4 (an improved version of the N5 family) scheduled for 2022, they must complete research and development within this year and have to start risk production. That means they seem to be unable to catch up with 3nm.

Every year, TSMC must continue to develop and mass produce for Apple because, as shown in Figure 13, TSMC's sales to Apple account for 25%, and Apple is TSMC's largest customer.

Figure 13. Share of TSMC sales (2020)

Moore's Law is the "Law of Human Desire"

Let's calculate how difficult it is to manufacture 100 million APs in the most advanced logic devices. The A13 chip manufactured for the iPhone 11 in 2019 has a size of 98.48mm². Calculated from a 12-inch wafer, it is 707, and if the yield is set to 90% (which I think is not too high), it is 636.

In this case, if 100 million units are manufactured, about 1.5 million wafers must be invested. The A13 is manufactured using 7nm (N7) without EUV, and it is said that the monthly manufacturing capacity of N7 is about 150K (150,000) 12-inch wafers. Therefore, TSMC must fully operate the N7 production line within 10 months for the A13. During this period, AMD's CPU, NVIDIA's GPU, MediaTek's AP, and Qualcomm's baseband chips have no chance to enter.

As a result, the most advanced logic devices every year are almost monopolized by Apple's AP, and after the turmoil is over, other FABLESS' cutting-edge products have to be manufactured.

On the other hand, TSMC's largest customer, Apple, requests AP manufacturing in the most advanced process every year, so TSMC develops this logic device, and due to its most advanced process, other fabs (although a little late) can benefit from it, that is, produce cutting-edge chips.

From this situation, it can be said that the reason why TSMC can continue to be the most advanced in the world is because of the Christmas shopping war in the United States. In other words, how many new iPhones will Apple sell every December, or whether Americans are willing to buy this new iPhone. In other words, the driving force behind TSMC's "running on the country road at a speed of 100 kilometers per hour" is that Americans want to buy iPhones with "higher performance, easier to use, and longer battery life."

In short, TSMC's advancement shows that Moore's Law is the law of human desire. (More precisely, American desire?)

Even if scaling stops, Moore's Law won't end

Even after explaining the above, many people still argue, "If refinement becomes atomic level, calibration will stop." However, even so, I still insist, "Moore's Law will continue even if refinement becomes atomic level and stops."

At the 2019 VLSI Symposium, Mr. Robert D. Clark (Tokyo Electron Technology Center) gave a speech titled "Selective and Self-Limited Thein Film Process for the Atomic Scale Era". Although he did not have any configuration materials at the Sunday Workshop, I was deeply moved by one of Robert D. Clark's slides.

Figure 14. The vertical axis is computing speed, and Moore's Law has continued for 120 years.

"Moore's Law" advocated by Gordon E. Moore, one of the founders of Intel, explains that the integration of transistors has doubled in two years. However, Robert D. Clark explained in Figure 14 that if the vertical axis is not the integration of transistors but the speed of computers, then "Moore's Law has lasted for 120 years from 1900 to the present."

The 7nm, 5nm, and 3nm technology nodes mentioned by TSMC before are just product names, and their sizes cannot be found anywhere on the chip. On the contrary, with the development of the times, the power is reduced, the high speed and other performance are improved, the transistor size (or footprint) is reduced, and the chip size is smaller. In other words, Power, Performance, Area (PPA) is improved.

Therefore, even if scaling stops, Moore's Law will not end as long as one of the PPAs is advancing.

Summarize

Well, let me summarize this long topic. First of all, miniaturization cannot be stopped until at least 2030. This is basically the same as the prediction of a TSMC executive in 2007 that "hp10nm is the limit". In addition, because lithography experts are always pessimistic, their words are not very credible. The evidence is that the EUV lithography machine manufacturing that was "absolutely impossible to mass produce" has been realized.

Furthermore, TSMC is now scaling down like crazy, so the driving force behind the continuation of Moore's Law is not anything else but "human desire". Therefore, as long as humans continue to have desire, they will not stop miniaturization for the time being. Moreover, even if the scaling stops at the atomic level, if the parameters other than the integration of transistors (such as the speed of computers) are set as the vertical axis, Moore's Law may continue until the extinction of mankind.

Therefore, from the current perspective, the biggest challenge for semiconductor miniaturization and Moore's Law is to defeat the new coronavirus that has mutated into Delta.

*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.

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