[ShiShuo Design] It is necessary to have a comprehensive understanding of different types of switching regulator noise!

This section introduces the buck converter output ripple calculation formula based on fundamental and harmonic theory. Ripple is always the main noise in switching regulators, because the peak-to-peak voltage amplitude is generally a few mV to tens of mV, depending on the switching regulator topology and basic operation. It should be regarded as a periodic and predictable signal. If it works at a fixed switching frequency, it is easy to identify and measure it in the time domain through an oscilloscope or in the frequency domain through Fourier decomposition.

Figure 1 shows a typical buck regulator. The two switches are turned on and off alternately, so the SW node voltage VSW is an ideal square wave, and this characteristic is further transferred to the duty cycle and input voltage. VSWVSW can be expressed by the following formula:

Figure 1. Buck regulator topology.

Where:
VIN is the input voltage. D is the duty cycle; for a buck regulator, it is equal to VOUT/VIN

Once VIN is determined, the VSW fundamental and harmonic components depend only on the duty cycle. Figure 2 shows the VSW fundamental and harmonic amplitudes as a function of duty cycle. When the duty cycle is close to half, the ripple amplitude is dominated by the fundamental.

Figure 2. Buck regulator VSWW amplitude vs. duty cycle.

The buck regulator output LC stage transfer function is as follows:

Where L is the output inductance, DCR is the inductor resistance, and CL is the inductor parallel capacitance.

COUT is the output capacitance value. ESL is the capacitor series inductance value. ESR is the capacitor series resistance value.

Therefore, VOUT can be expressed as follows:

To simplify the calculations, we assume an output LC stage of 20 dB/decade, and then the VOUT ripple fundamental and harmonic amplitudes related to duty cycle are shown in Figure 3. When the duty cycle approaches half, the third or odd harmonics will be higher than the even harmonics. Due to LC suppression, the higher harmonics will have lower amplitudes and will be a very small proportion compared to the total ripple amplitude. Again, the fundamental amplitude is the dominant component in the switching regulator output ripple.

Figure 3. Buck regulator VOUT ripple amplitude vs. duty cycle.

For a buck regulator, the fundamental amplitude is related to the input voltage, duty cycle, switching frequency, and LC stage; however, all of these parameters affect application requirements such as efficiency and solution size. To further reduce the ripple, adding a post filter is recommended.

Broadband noise in a switching regulator is random amplitude noise on the output voltage. It can be expressed as noise density over the entire frequency range in V/√Hz z, or as Vrms, which is inseparable from the density over the frequency range. Due to limitations in silicon process and reference voltage source filter design, broadband noise is primarily located in the 10Hz to 1MHz frequency range of the switching regulator, and it is difficult to reduce it by adding filters in the low frequency range.

The peak-to-peak amplitude voltage of a typical buck regulator broadband noise is about 100μV to 1000μV, which is much lower than the switching ripple noise. If an additional filter is used to reduce the switching ripple noise, the broadband noise may become the dominant noise of the switching regulator output voltage. Figure 4 shows that when there is no additional filter, the dominant source of the buck regulator output noise is the switching ripple. Figure 5 shows that when an additional filter is used, the dominant source of the output noise is the broadband noise.

Figure 4. VOUT without additional filter.

Figure 5. VOUT with additional filter.

(Measured using a 1000x preamplifier)

In order to identify and analyze the switching regulator output broadband noise, the regulator control scheme and module noise information must be obtained. For example, Figure 6 shows a typical current mode buck regulator control scheme and module noise source injection.

Figure 6. Typical current-mode buck regulator control scheme.

For the control loop transfer function and module noise characteristic information obtained, there are two different types of noise: loop input noise and in-loop noise. The loop input noise within the control loop bandwidth is transferred to the output, while the noise outside the loop bandwidth is attenuated. For switching regulators, it is critical to design low-noise EA and reference voltage sources because the unity feedback gain keeps the noise level constant instead of increasing it as the output voltage level increases. The biggest challenge is to find the largest noise source in the entire system and reduce it in the circuit design. The ADP5014 is optimized for low noise technology and uses a current mode control scheme and a simple LC external filter to achieve noise performance below 20μVrms in the frequency range of 10Hz to 1MHz. The output noise performance of the ADP5014 is shown in Figure 7.

Figure 7. ADP5014 output noise performance with additional LC filter.

The third type of noise is high-frequency spike and ringing noise because the output voltage is generated by the switching regulator turn-on or turn-off transient. Consider the parasitic inductance and capacitance in the silicon circuit and PCB traces; for the buck regulator, the fast current transient will cause high-frequency voltage spikes and ringing at the SW node. The spike and ringing noise will increase with the increase of current load. Figure 8 shows how the buck regulator forms spikes. Depending on the turn-on/off slew rate of the switching regulator, the highest spike and ringing frequency will be in the range of 20MHz to 300MHz, and the output LC filter may not be very effective in suppressing it due to the parasitic inductance and capacitance. Compared with all the above discussions about the conduction path, the worst is the radiated noise from the SW and VIN nodes. Since its frequency is very high, the output voltage and other analog circuits will be affected.

Figure 8. Buck regulator high frequency spike and ringing noise.

To reduce high-frequency spike and ringing noise, effective methods are recommended for application and chip design. First, additional LC filters or beads should be used on the terminal load. Generally, this will make the spike noise on the output much smaller than the ripple noise, but will increase higher frequency components. Second, the noise sources of the SW and input nodes should be shielded or kept away from the output side and sensitive analog circuits, and the output inductor should be shielded. Careful layout and routing are important for the design. Third, optimize the on/off slew rate of the switching regulator and minimize the parasitic inductance and resistance of the switching regulator to effectively reduce the SW node noise. ADI SilentSwitchr® technology also helps to reduce the VIN node noise through chip design.

PSRR reflects the ability of a switching regulator to suppress input power supply noise from being transmitted to the output. This section analyzes the buck regulator PSRR performance in the low frequency range. High frequency noise affects the output voltage mainly through the radiation path, rather than through the conduction path discussed previously.

Based on the buck small signal graph shown in Figure 9, the buck PSRR can be expressed as follows:

Figure 9. Current-mode buck small signal plot from input voltage to output.

in:

Compare the signal mode calculations with the simulation results. The small signal mode is valid and consistent with the simulation results.

The PSRR performance of a switching regulator depends on the loop gain performance in the low frequency range. The inherent LC filter of the switching regulator can suppress input noise in the mid-frequency range (100Hz to 10MHz). The suppression performance in this range is much better than the LDO PSRR. Therefore, the switching regulator has an ideal PSRR performance because it has a high loop gain at low frequencies, while the inherent LC filter affects the mid-frequency range.

Figure 10. PSRR calculation results using buck small signal mode.

Figure 11. PSRR simulation in SIMPLIS mode

More and more analog circuits, such as ADC/DAC, clocks, and PLLs, require clean power supplies that can provide high current. Each device requires a clean power supply that can provide high current for C/DAC, clocks, and PLLs in different frequency ranges. Each device has different requirements and specifications for power supply noise in different frequency ranges. It is necessary to fully understand the different types of switching regulator noise and recognize the power supply noise requirements to design and implement high-efficiency, low-noise switching regulators to meet the low noise specifications of most analog circuit power supplies. Compared with LDO regulators, this low-noise switching solution will have higher power efficiency, smaller solution size, and lower cost.