PIC18F27/47/57Q43
28/40/44/48-Pin, Low-Power, High-Performance
Microcontroller with XLP Technology
Introduction
The PIC18-Q43 microcontroller family is available in 28/40/44/48-pin devices for real-time control applications. This
family features a 12-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for
advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison. This family
showcases a new 16-bit PWM module which provides dual independent outputs on the same time base. Additional
features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct
Memory Access (DMA) capabilities, UART with support for asynchronous, DMX, DALI and LIN protocols, SPI, I
2
C,
memory features like Memory Access Partition (MAP) to support users in data protection and bootloader applications,
and Device Information Area (DIA), which stores factory calibration values to help improve temperature sensor
accuracy.
PIC18-Q43 Family Types
Table 1. Devices included in this data sheet
Direct Memory Access (DMA)
UART/
UART with Protocol Support
Windowed Watchdog Timer
Signal Measurement Timer
Peripheral Module Disable
Y
Y
Y
Complimentary Waveform
Generator
Memory Access Partition/
Device Information Area
16-Bit CRC with Scanner
High-Low Voltage Detect
Configurable Logic Cell
12-Bit ADCC (channels)
Program Memory Flash
(bytes)
Numerically Controlled
Oscillator
Temperature Indicator
Y
Y
Y
I/O Pins/
Peripheral Pin Select
8-Bit Timer with HLT/
16-Bit Timers
PIC18F27Q43
PIC18F47Q43
PIC18F57Q43
128k
128k
128k
8192
8192
8192
1024
1024
1024
Y/Y
Y/Y
Y/Y
25/Y
36/Y
44/Y
3/4
3/4
3/4
3/3
3/3
3/3
3
3
3
1
1
1
3
3
3
8
8
8
24
35
43
1
1
1
2/1
2/1
2/1
1
1
1
2/1
2/1
2/1
4/1
4/1
4/1
6
6
6
Y
Y
Y
Y
Y
Y
©
2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002147D-page 1
Vectored Interrupts
Y
Y
Y
Comparator/
Zero-Cross Detect
16-Bit Dual PWM/
CCP
Data EEPROM
(bytes)
Data SRAM
(bytes)
8-Bit DAC
SPI/I2C
Device
PIC18F27/47/57Q43
Table 2. Devices not included in this data sheet
Direct Memory Access (DMA)
UART/
UART with Protocol Support
Windowed Watchdog Timer
Signal Measurement Timer
Peripheral Module Disable
Y
Y
Y
Y
Y
Y
Complimentary Waveform
Generator
Memory Access Partition/
Device Information Area
16-Bit CRC with Scanner
High-Low Voltage Detect
Configurable Logic Cell
12-Bit ADCC (channels)
Program Memory Flash
(bytes)
Numerically Controlled
Oscillator
Temperature Indicator
Y
Y
Y
Y
Y
Y
I/O Pins/
Peripheral Pin Select
8-Bit Timer with HLT/
16-Bit Timers
PIC18F25Q43
PIC18F26Q43
PIC18F45Q43
PIC18F46Q43
PIC18F55Q43
PIC18F56Q43
32k
64k
32k
64k
32k
64k
2048
4096
2048
4096
2048
4096
1024
1024
1024
1024
1024
1024
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
25/Y
25/Y
36/Y
36/Y
44/Y
44/Y
3/4
3/4
3/4
3/4
3/4
3/4
3/3
3/3
3/3
3/3
3/3
3/3
3
3
3
3
3
3
1
1
1
1
1
1
3
3
3
3
3
3
8
8
8
8
8
8
24
24
35
35
43
43
1
1
1
1
1
1
2/1
2/1
2/1
2/1
2/1
2/1
1
1
1
1
1
1
2/1
2/1
2/1
2/1
2/1
2/1
4/1
4/1
4/1
4/1
4/1
4/1
6
6
6
6
6
6
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Features
•
•
C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 64 MHz clock input
– 62.5 ns minimum instruction cycle
Six Direct Memory Access (DMA) Controllers:
– Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR
spaces
– User programmable source and destination sizes
– Hardware and software triggered data transfers
Vectored Interrupt Capability:
– Selectable high/low priority
– Fixed interrupt latency of three instruction cycles
– Programmable vector table base address
– Backwards compatible with previous interrupt capabilities
127-Level Deep Hardware Stack
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
– Watchdog Reset on too long or too short interval between watchdog clear events
– Variable prescaler selection
– Variable window size selection
•
•
•
•
•
•
•
•
Memory
•
•
•
•
Up to 128 KB of Program Flash Memory
Up to 8 KB of Data SRAM Memory
1024 Bytes Data EEPROM
Memory Access Partition: The Program Flash Memory can be partitioned into:
– Application Block
– Boot Block
– Storage Area Flash (SAF) Block
©
2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002147D-page 2
Vectored Interrupts
Y
Y
Y
Y
Y
Y
Comparator/
Zero-Cross Detect
16-Bit Dual PWM/
CCP
Data EEPROM
(bytes)
Data SRAM
(bytes)
8-Bit DAC
SPI/I2C
Device
PIC18F27/47/57Q43
•
•
Programmable Code Protection and Write Protection
Device Information Area (DIA) Stores:
– Temperature indicator factory calibrated data
– Fixed Voltage Reference measurement data
– Microchip unique identifier
Device Characteristics Information (DCI) Area Stores:
– Program/erase row sizes
– Pin count details
– EEPROM size
Direct, Indirect and Relative Addressing modes
•
•
Operating Characteristics
•
•
Operating Voltage Range:
– 1.8V to 5.5V
Temperature Range:
– Industrial: -40°C to 85°C
– Extended: -40°C to 125°C
Power-Saving Functionality
•
•
•
•
•
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
– Ability to selectively disable hardware module to minimize active power consumption of unused peripherals
Low-Power Mode Features:
– Sleep: < 800nA typical @ 1.8V
– Operating Current:
• 48µA @ 32 kHz, 3V, typical
Digital Peripherals
•
Three 16-Bit Pulse-Width Modulators (PWM):
– Dual outputs for each PWM module
– Integrated 16-bit timer/counter
– Double-buffered user registers for duty cycles
– Right/Left/Center/Variable aligned modes of operation
– Multiple clock and Reset signal selections
Four 16-Bit Timers (TMR0/1/3/5)
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Eight Configurable Logic Cell (CLC):
– Integrated combinational and sequential logic
Three Complimentary Waveform Generators (CWG):
– Rising and falling edge dead-band control
– Full-bridge, half-bridge, 1-channel drive
– Multiple signal sources
– Programmable dead band
– Fault-shutdown input
•
•
•
•
©
2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002147D-page 3
PIC18F27/47/57Q43
•
Three Capture/Compare/PWM (CCP) modules:
– 16-bit resolution for Capture/Compare modes
– 10-bit resolution for PWM mode
Three Numerically Controlled Oscillators (NCO):
– Generates true linear frequency control and increased frequency resolution
– Input clock up to 64 MHz
Signal Measurement Timer (SMT):
– 24-bit timer/counter with prescaler
– Several modes of operation like Time-of-Flight, Period and Duty Cycle measurement etc.
Data Signal Modulator (DSM):
– Multiplex two carrier clocks, with glitch prevention feature
– Multiple sources for each carrier
Programmable CRC with Memory Scan:
– Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
– Calculate 16-bit CRC over any portion of Program Flash Memory
Five UART modules:
– One module (UART1) supports LIN master and slave, DMX mode, DALI gear and device protocols
– Asynchronous UART, RS-232, RS-485 compatible
– Automatic and user timed BREAK period generation
– Automatic checksums
– Programmable 1, 1.5, and two Stop bits
– Wake-up on BREAK reception
– DMA compatible
Two SPI modules:
– Configurable length bytes
– Arbitrary length data packets
– Transmit-without-receive and receive-without-transmit option
– Transfer byte counter
– Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
One I
2
C module, SMBus, PMBus
™
Compatible:
– 7-bit and 10-bit addressing modes with address masking modes
– Dedicated address, transmit and receive buffers and DMA capabilities
– Bus collision detection with arbitration
– Bus time-out detection and handling
– I
2
C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
– Multi-Master mode, including self-addressing
Device I/O Port Features:
– 25 I/O pins (PIC18F25/26/27Q43)
– 36 I/O pins (PIC18F45/46/47Q43)
– 44 I/O pins (PIC18F55/56/57Q43)
– Individually programmable I/O direction, open-drain, slew rate and weak pull-up control
– Interrupt-on-change on most pins
– Three programmable external interrupt pins
Peripheral Pin Select (PPS):
– Enables pin mapping of digital I/O
•
•
•
•
•
•
•
•
•
Analog Peripherals
•
Analog-to-Digital Converter with Computation (ADCC):
©
2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002147D-page 4
PIC18F27/47/57Q43
– Up to 140 KSPS
– Up to 43 external channels
– Automated math functions on input signals:
• Averaging, filter calculations, oversampling and threshold comparison
– Operates in Sleep
– Five internal analog channels
– Hardware Capacitive Voltage Divider (CVD) Support:
• Adjustable sample-and-hold capacitor array
• Guard ring digital output drive
• Automates touch sampling and reduces software size and CPU usage when touch or proximity
sensing is required
8-Bit Digital-to-Analog Converter (DAC):
– Buffered output available on two I/O pins
– Internal connections to ADC and Comparators
Two Comparators (CMP):
– Four external inputs
– Configurable output polarity
– External output via Peripheral Pin Select
Zero-Cross Detect (ZCD):
– Detect when AC signal on pin crosses ground
Voltage Reference:
– Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels
– Internal connections to ADC, Comparator and DAC
•
•
•
•
Clocking Structure
•
High-Precision Internal Oscillator Block (HFINTOSC):
– Selectable frequencies up to 64 MHz
– ±1% at calibration
– Active Clock Tuning of HFINTOSC for better accuracy
31 kHz Low-Power Internal Oscillator (LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External High-frequency Oscillator Block:
– Three crystal/resonator modes
– Digital Clock Input mode
– 4x PLL with external sources
Fail-Safe Clock Monitor:
– Allows for operational recovery if external clock stops
Oscillator Start-up Timer (OST):
– Ensures stability of crystal oscillator sources
•
•
•
•
•
Programming/Debug Features
•
•
•
In-Circuit Serial Programming
™
(ICSP
™
) via Two Pins
In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
Debug Integrated On-Chip
©
2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002147D-page 5
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