[Project source code] FPGA-based asynchronous FIFO show-ahead mode

小梅哥

[Project source code] FPGA-based asynchronous FIFO show-ahead mode [Copy link]

 

I recently used an asynchronous FIFO and found the show-ahead mode very interesting. As shown in the figure below, after simulating the FIFO IP core, you can see that the data is written two clock cycles after the rising edge of the write request signal, and the FIFO output end has data output three clock cycles later, without the need for a read request signal. However, the data at the output end will only be updated when a read request signal is issued, and will be updated immediately after the rising edge of the read signal arrives (one clock cycle faster than the normal mode). See the figure below:

However, I encountered a very frustrating phenomenon when using asynchronous FIFO. The FIFO input data width is 24 bits. I plan to set the output data width to 4 bits, but the software will show that the width is invalid. I checked the information and found that the input and output width of FIFO must be a multiple of the power of 2, otherwise it will cause redundant data inside the FIFO. I had no choice but to change the output width and then split the output data. I wonder if there is a better way.