When selecting devices, we often make trade-offs on the technical indicators on the DATASHEET. After all, not every technical indicator will affect the system goals we want to achieve. For ADC, the signal-to-noise ratio (SNR) is undoubtedly the focus of people's attention.
So, apart from the signal-to-noise ratio, what impact will other technical indicators have on our system?
Resolution, perhaps the most misunderstood specification, indicates the number of output bits but does not provide performance data. Some data sheets list the effective number of bits (ENOB), which uses actual SNR measurements to calculate the effectiveness of the converter. A more useful converter performance metric is the noise spectral density (NSD), which is expressed in dBm/Hz or HznV. NSD can be calculated (dBm/Hz) from a known sampling rate, input range, SNR, and input impedance. Knowing these parameters, a converter can be selected to match the analog performance of the front-end circuitry, which is a more effective way to select an ADC than simply listing the resolution.
Many users also consider spurious and harmonic performance, which are independent of resolution, but converter designers typically adjust their designs to make harmonics consistent with resolution.
02Power Supply Rejection (PSR)
Power supply rejection (PSR) measures how power supply ripple couples to the ADC input and appears at its digital output. If PSR is finite, noise on the power supply line will only be rejected by 30 to 50 dB relative to the input level.
Generally speaking, the unwanted signal on the power supply is related to the input range of the converter. For example, if the noise on the power supply is 20 mV rms and the converter input range is 0.7 Vrms, then the noise on the input is –31 dBFS. If the converter has a PSR of 30 dB, the coherent noise will show up as a –61 dBFS line at the output. PSR is especially useful in determining how much filtering and decoupling a power supply will require, which is important in high noise environments such as medical or industrial applications.
Figure 1. Power Supply Ripple Rejection Ratio (PSRR) vs. Frequency
03Common Mode Rejection (CMR)
Common-mode rejection (CMR) measures the differential-mode signal induced in the presence of a common-mode signal. Many ADCs use differential inputs to achieve high immunity to common-mode signals because the differential input structure inherently rejects even-order distortion products.
As with PSR, common-mode signals can be introduced by power supply ripple, high power signals generated on the ground plane, RF leakage from mixers and RF filters, and applications that can generate high electric and magnetic fields. Although many converters do not specify CMR, they typically have a CMR of 50 to 80 dB.
04Clock related technical indicators
Clock-related specifications, although important, are not always specified and can be difficult to determine.
Figure 2. Input clock vs. sampling noise.
The clock slew rate is the minimum slew rate required to achieve the specified performance. Most converters have enough gain on the clock buffer to ensure that the sampling instant is well defined, but if the slew rate is too low so that the sampling instant is very uncertain, excessive noise will be generated. If a minimum input slew rate is specified, the user should meet this requirement to ensure the specified noise performance.
Aperture jitter is the internal clock uncertainty of the ADC. The noise performance of the ADC is limited by the internal and external clock jitter.
In a typical data sheet, aperture jitter is limited to the converter. External aperture jitter is added to the internal aperture jitter in an RMS manner. For low frequency applications, jitter may not be important, but as analog frequencies increase, noise issues caused by jitter become more and more significant. If an adequate clock is not used, performance will be worse than expected.
In addition to the noise added by clock jitter, spectral lines in the clock signal that have no harmonic relationship with the clock will also appear as distortion in the digitized output. Therefore, the clock signal should have the highest possible spectral purity.
孔径延迟是采样信号的应用与实际进行输入信号采样的时刻之间的时间延迟。此时间通常为纳秒或更小，可能为正、为负或甚至为零。除非知道精确的采样时刻非常重要，否则孔径延迟并不重要。
07Conversion time and conversion delay
Conversion time and conversion latency are two closely related specifications. Conversion time generally applies to successive approximation converters (SAR), which use a high clock rate to process the input signal, and the input signal appears at the output significantly later than the conversion command, but earlier than the next conversion command. The time between the conversion command and the completion of the conversion is called the conversion time.
Conversion delay is often applied to pipelined converters. As a measure of the number of pipelines (internal digital stages) used to produce the digital output, conversion delay is usually specified in terms of pipeline delay. By multiplying this number by the sampling period used in the application, the actual conversion time can be calculated.
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