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Cadence launches Conformal Litmus solution - the fastest path to full-chip constraints and CDC signoff

Latest update time:2019-07-25
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New generation constraint sign-off and CDC sign-off solution

Can speed up turnaround time by 10 times, with sign-off timer accuracy reaching 100%



Shanghai, China, July 24, 2019 - Cadence Electronics (Cadence, Inc., NASDAQ: CDNS) today released a new generation of Cadence Conformal Litmus solution that supports constrained signoff and cross-clock domain (CDC) signoff, which not only helps In addition to shortening the overall design cycle, it can also improve the quality of silicon wafers in complex SoC designs. Compared with the previous generation solution, Conformal Litmus can achieve 100% sign-off timer accuracy and turnaround time is 10 times faster. To learn more about Cadence Conformal Litmus solutions, please click on the lower left corner to read the original article.


The new Conformal Litmus provides customers with the following features


The industry's first sign-off static timer integration solution:

Based on this integration, Conformal Litmus can accurately model designs and constraints using the same interpreter as the TempusÔ timing signoff solution, providing customers with 100% register transfer level (RTL) signoff accuracy.

CDC structure signoff:

Used to verify the correctness of the CDC structure in the design from the early RTL stage to the design implementation process. Intelligent analysis and reporting capabilities provide rapid sign-off capabilities, helping customers save weeks to months of design time.

Constraint signoff:

It is used to check the correctness and completeness of module-level constraints, and allows users to perform consistency checks on sub-modules and top-level module constraints when doing SoC integration. Conformal Litmus intelligent analysis can generate accurate and clear reports, shorten debugging time, and help users quickly obtain sign-off-quality constraints.

Multi-CPU parallelism:

Multiple cores can be leveraged to perform parallel verification, accelerating SoC design turnaround time by 10 times.


As design complexity increases, accelerating SoC delivery to meet tight project schedules while reducing development costs remains an increasingly difficult challenge," said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence." The innovative features of the new Cadence Conformal Litmus solution can help customers achieve constraints and CDC sign-off, and achieve reliable, high-quality design tape-out on time.


The Conformal Litmus solution is part of Cadence's full digital and signoff product offering, providing a more predictive and faster design closure path. It also supports Cadence Intelligent System Design™ strategy to help achieve excellent IP and SoC design.



success case


- Hideyuki Okabe, Director of Digital Design Technology Department, Renesas Electronics

"The Cadence Conformal Litmus solution supports multi-CPU parallel processing, and we can complete a complete run of a large 50 million instance-level design in 10 hours. The solution provides us with the accuracy, speed and rapid debugging capabilities we need to help design and The implementation team completed the tapeout iteratively with the least constrained quality.”

- Vikram Kuralla, Director of Engineering at Invecas

“Our goal is to provide customers with silicon-proven IP and stable design methods to help ASIC designers meet the challenges of increased design complexity, higher costs and shorter development cycles, and help achieve first-time success in silicon design. The IP and ASICs we develop have extremely complex CDC structures, including handshake synchronizers, bus synchronizers, and FIFOs. CDC signoff is often cumbersome because the engineers responsible for CDC verification have little idea of ​​the design intent; Cadence Conformal Litmus can Through comprehensive analysis, it is presented in a very intuitive way, providing the powerful capabilities needed to understand CDC intentions and timing constraint checks at the RTL level, helping us achieve rapid sign-off and significantly shorten design time.”

- Susumu Abe, General Manager of Semiconductor IP and R&D Department, Processor Development Division, NSITEXE Corporation

“We develop, create and license efficient, high-quality semiconductor IP for automotive, industrial and other applications. To ensure our IP is fully validated and ready for delivery, CDC sign-off is key. After evaluating Cadence Conformal Litmus, we We are impressed by its CDC capabilities, especially its intelligent analysis and reporting, which can help us quickly identify missing, invalid and incorrect CDC synchronization solutions in the design, and greatly speed up CDC sign-off with its keen diagnostic capabilities. process."



About Cadence



Cadence Corporation is committed to enabling electronic systems and semiconductor companies to design innovative end products that change the way people work, live and play. Customers use Cadence's software, hardware, IP and services, covering everything from semiconductor chips to circuit board design and even entire systems, to help them deliver products to the market faster. Cadence's innovative "Intelligent System Design" strategy will help customers develop more differentiated products, whether in mobile devices, consumer electronics, cloud computing data centers, automotive electronics, aviation, the Internet of Things, Industrial applications and other application markets. Cadence was also selected as one of the "100 Best Companies to Work for in the World" by Fortune magazine. To learn more, please visit the company's website at www.cadence.com.




© 2019 Cadence Design Systems, Inc. All rights reserved. All rights reserved worldwide. Cadence, the Cadence logo and other Cadence marks listed at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other marks are the property of their respective owners.


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