Reduce the pressure of hardware development, do you know this solution?

The electronics industry is changing rapidly, and with increasingly tight controls on R&D budgets and time to market (TTM), there is less time to build analog circuits and prototype them to verify their functionality. Hardware designers need to provide advanced precision data conversion performance and higher robustness through complex designs that are shrinking in size, while being limited by thermal performance and printed circuit board (PCB) density. Heterogeneous integration, enabled by system-in-package (SiP) technology, continues to drive the electronics industry's trend toward higher density, more functionality, higher performance, and longer mean time between failures. This article will describe how ADI is using heterogeneous integration to change the precision conversion playing field and provide solutions that have a significant impact on applications.

System designers face many challenges, not only need to select components and optimize the design for the final prototype, but also meet the technical requirements of driving ADC inputs, protecting ADC inputs from overvoltage events, minimizing system power consumption, and achieving higher system throughput with low-power microcontrollers and/or digital isolators. As OEMs focus more on system software and applications to create unique system solutions, they also allocate more resources to software development rather than hardware development. This increases the pressure on hardware development and requires further reduction of design iterations.

System designers developing data acquisition signal chains often require high input impedance to directly interface with a variety of sensors that may have varying common-mode voltages and unipolar or bipolar single-ended or differential input signals. A thorough analysis of a typical signal chain implemented using discrete components will provide some of the key technical challenges for system designers, as shown in Figure 2. The key portion of a precision data acquisition subsystem is shown, where a 20 V pp instrumentation amplifier output is applied to the noninverting input of a fully differential amplifier (FDA). This FDA provides the necessary signal conditioning, including level shifting, signal attenuation, and an output swing between 0 V and 5 V with an output common-mode voltage of 2.5 V and opposite phases, providing a 10 V pp differential signal to the ADC input to maximize its dynamic range. The instrumentation amplifier is powered by a dual supply of ±15 V, while the FDA is powered by +5 V/–1 V and the ADC is powered by a 5 V supply. The FDA gain is set to 0.5 using the ratio of the feedback resistor (RF1 = RF2) to the gain resistor (RG1 = RG2). The noise gain (NG) of the FDA is defined as:

Where β1 and β2 are feedback coefficients:

This section will explore how circuit imbalance (i.e., β1 ≠ β2) or mismatch of feedback and gain resistors (R _G1 , R _G2 , R _F1 , R _F2 ) around the FDA affects key technical parameters such as SNR, distortion, linearity, gain error, offset, and input common-mode rejection ratio. The differential output voltage of the FDA depends on V _OCM , so when the feedback factors β1 and β2 are not equal, any imbalance in the output amplitude or phase will produce undesirable common-mode components at the output, which, after being amplified by the noise gain, will cause redundant noise and offset in the differential output of the FDA. Therefore, the ratio of gain/feedback resistors must be matched. In other words, the combination of input source impedance and R _G2 (R _G1 ) should be matched (i.e., β1 = β2) to avoid signal distortion and common-mode voltage mismatch of each output signal, and to prevent the common-mode noise of the FDA from increasing. To cancel the differential offset and avoid output distortion, an external resistor in series with the gain resistor (R _G1 ) can be added. Moreover, the gain error offset is also affected by the resistor type, such as thin film, low temperature coefficient resistors, etc., and it is not easy to find matching resistors under the constraints of cost and board space.

In addition, many designers have trouble creating a single bipolar power supply due to additional cost and limited space on the PCB. Designers also need to carefully select the appropriate passive components, including RC low-pass filters (placed between the ADC driver output and the ADC input) and decoupling capacitors for the dynamic reference node of the successive approximation register (SAR) ADC. The RC filter helps limit the noise at the ADC input and reduces the kickback from the capacitive DAC at the input of the SAR ADC. C0G or NP0 type capacitors and reasonable series resistor values ​​should be selected to keep the amplifier stable and limit its output current. Finally, PCB layout is critical to maintaining signal integrity and achieving the expected performance of the signal chain.

Many system designers end up designing different signal chain architectures for the same application. However, not all designs are suitable for the same signal chain, so ADI provides complete signal chain µModule ^® solutions with advanced performance, focusing on the common parts of the signal chain, signal conditioning, and digitization to bridge the gap between standard discrete devices and highly integrated customer-specific ICs and help solve major pain points. The ADAQ4003 is a SiP solution that takes into account the two factors of reducing R&D costs and reducing size while accelerating prototyping.

The ADAQ4003 µModule precision data acquisition solution uses ADI’s advanced SiP technology to integrate multiple common signal processing and conditioning blocks and key passive components into a single device (see Figure 5). The ADAQ4003 includes a low noise, FDA, stable reference buffer, and a high resolution 18-bit, 2 MSPS SAR ADC.

The ADAQ4003 simplifies signal chain design, shortens the development cycle of precision measurement systems, and solves all the major issues discussed in the previous section by transferring component selection, optimization, and layout from the designer to the device itself. The precision resistor array around the FDA is built using ADI's proprietary i Passives® ^technology to solve circuit imbalance problems, reduce parasitic effects, help achieve excellent gain matching up to 0.005%, and optimize drift performance (1 ppm/°C). iPassives technology also has size advantages compared to discrete passive components, thereby minimizing temperature-related error sources and reducing system-level calibration efforts. The FDA provides fast settling and wide common-mode input range and precise configurable gain options (0.45, 0.52, 0.9, 1, or 1.9) performance, allowing gain or attenuation adjustment, supporting fully differential or single-ended to differential.

The ADAQ4003 is configured with a single-pole RC filter between the ADC driver and the ADC to minimize settling time and maximize input signal bandwidth. In addition, all necessary decoupling capacitors are provided for the reference voltage node and power supply to simplify the bill of materials (BOM). The ADAQ4003 also has a built-in reference voltage buffer configured for unity gain to drive the dynamic input impedance of the SAR ADC reference voltage node and the corresponding decoupling capacitors to achieve optimized performance. The 10 µF on the REF pin is a key requirement to help replenish the charge of the internal capacitor DAC during the bit judgment process, which is critical to achieving peak conversion performance. Compared to many traditional SAR ADC signal chains, with the built-in reference voltage buffer, users can achieve a lower power reference voltage source because the reference voltage source drives a high impedance node instead of the dynamic load of the SAR capacitor array. And there is flexibility in selecting the reference voltage buffer input voltage that matches the required analog input range.

The ADAQ4003’s 7 mm × 7 mmBGA package is at least 4 times smaller than a traditional discrete signal chain (see Figure 3), enabling small instrumentation without sacrificing performance.

Printed circuit board layout is critical to maintaining signal integrity and achieving the expected performance of the signal chain. The pinout of the ADAQ4003, with analog signals on the left and digital signals on the right, simplifies layout. In other words, this allows designers to keep sensitive analog and digital sections separate and confined to certain areas of the board, avoiding crossover of digital and analog signals to mitigate radiated noise. The ADAQ4003 integrates all necessary (low equivalent series resistance (ESR) and low equivalent series inductance (ESL)) decoupling ceramic capacitors for the reference (REF) and power supply (VS+, VS−, VDD, and VIO) pins. These capacitors provide a low impedance path to ground at high frequencies to handle transient currents.

No external decoupling capacitors are required, and without them, there is no known performance impact or any EMI issues. This performance impact can be verified on the ADAQ4003 evaluation board by removing the external decoupling capacitors on the reference and LDO regulator outputs used to form the on-board power rails (REF, VS+, VS−, VDD, and VIO). Figure 4 shows that the stray noise is hidden below the noise floor of less than −120 dB, whether the external decoupling capacitors are used or removed. The small size of the ADAQ4003 allows for high channel density PCB layout while alleviating thermal challenges. However, the layout of the components and the routing of the various signals on the PCB are critical. It is particularly important to use symmetrical routing for input and output signals, and to keep the power supply circuits away from the analog signal paths on separate power planes and use as wide a trace as possible to provide low impedance paths, reduce the impact of glitch noise on the power supply lines, and avoid EMI issues.

As mentioned previously, a high input impedance front end is usually required to interface directly with various types of sensors. Most instrumentation and programmable gain instrumentation amplifiers (PGIAs) have single-ended outputs and cannot directly drive a fully differential data acquisition signal chain. However, the LTC6373 PGIA offers fully differential outputs, low noise, low distortion, and high bandwidth to directly drive the ADAQ4003 without sacrificing precision performance, making it suitable for many signal chain applications. The LTC6373 is DC coupled at both the input and output through programmable gain settings (using the A2, A1, and A0 pins).

In Figure 5, the LTC6373 is configured in a differential input to differential output configuration with ±15 V dual supplies. The LTC6373 can also be configured in a single-ended input to differential output configuration if desired. The LTC6373 directly drives the ADAQ4003, which is set for a gain of 0.454. The V _OCM pin of the LTC6373 is grounded, and its output swings between −5.5 V and +5.5 V (in opposite phase). The FDA of the ADAQ4003 level shifts the output of the LTC6373 to match the input common mode required by the ADAQ4003 and provides the signal amplitude required to utilize the maximum 2× V _REF peak differential signal range of the ADC within the ADAQ4003 μModule device. Figures 6 and 7 show the SNR and THD performance using various gain settings of the LTC6373, while Figure 8 shows the ±0.65 LSB/±0.25 LSB INL/DNL performance of the circuit configuration shown in Figure 5.

This section will focus on how the ADAQ4003 fits in ATE's source/sink and device power supplies. These modular instruments are used to test a variety of chip types for the fast-growing smartphone, 5G, automotive, and IoT markets. These precision instruments have current sourcing/sinking capabilities, and each channel that handles programmable voltage and current regulation requires a control loop, and they require high accuracy (especially good linearity), speed, wide dynamic range (for measuring µA/µV signal levels), monotonicity, and small size to accommodate the simultaneous increase in the number of channels. The ADAQ4003 provides excellent precision performance, which reduces the number of components in the end system and allows for increased channel density when board space is limited, while alleviating the calibration work and thermal challenges of such DC measurement scalable test instruments. The high accuracy of the ADAQ4003 combined with a fast sampling rate reduces noise and has no latency, making it ideal for control loop applications, providing excellent step response and fast settling time, thereby improving test efficiency. The ADAQ4003 helps reduce the design burden by eliminating the buffer that needs to allocate the reference voltage on the instrument due to its own drift and board space limitations. In addition, drift performance and component aging determine the accuracy of test instrumentation, so the deterministic drift of the ADAQ4003 reduces the cost of recalibration and reduces instrument downtime. The ADAQ4003 meets these requirements, enabling instruments to measure lower voltage and current ranges, helping to optimize control loops for various load conditions, thereby significantly improving the operating characteristics, test efficiency, throughput, and cost of the instrumentation. The high test throughput and short test time of these instruments will help end users reduce test costs. The SMU high-level block diagram is shown in Figure 9, and the corresponding signal chain is shown in Figure 5.

The high throughput rate enables oversampling of the ADAQ4003, which results in lower RMS noise and detection of small amplitude signals over a wide bandwidth. Oversampling the ADAQ4003 by a factor of 4 provides an additional 1 bit of resolution (this is because the ADAQ4003 provides adequate linearity, as shown in Figure 8), or an additional 6 dB of dynamic range, or in other words, the improvement in dynamic range due to this oversampling is defined as: ΔDR = 10 × log10 (OSR) in dB. The typical dynamic range of the ADAQ4003 is 100 dB at 2 MSPS with a 5 V reference and its inputs shorted to ground. Therefore, when the ADAQ4003 is oversampled by a factor of 1024 at an output data rate of 1.953 kSPS, it provides an excellent dynamic range of approximately 130 dB with gains of 0.454 and 0.9, allowing accurate detection of very small µV amplitude signals. Figure 10 shows the dynamic range and SNR of the ADAQ4003 at various oversampling rates and input frequencies of 1 kHz and 10 kHz.

This article introduces some important aspects and technical challenges related to designing precision data acquisition systems, and how ADI uses its linear and converter domain knowledge to develop a highly differentiated ADAQ4003 signal chain µModule solution to solve some difficult engineering design problems. The ADAQ4003 can ease engineering design work, such as device selection and building production-ready prototypes, enabling system designers to provide excellent system solutions to end customers faster.